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Commit 57520bc5 authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
Browse files

drm/i915: Merge the GEN9 memory latency PCU opcode with its friends 



Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 9043ae02

drivers/gpu/drm/i915/i915_reg.h

+5 −6
Original line number Diff line number Diff line
@@ -6648,6 +6648,11 @@ enum skl_disp_power_wells { 
#define	  GEN6_PCODE_READ_RC6VIDS		0x5

#define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)

#define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)

#define   GEN9_PCODE_READ_MEM_LATENCY		0x6

#define     GEN9_MEM_LATENCY_LEVEL_MASK		0xFF

#define     GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT	8

#define     GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT	16

#define     GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT	24

#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8

#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9

#define   GEN6_READ_OC_PARAMS			0xc
@@ -6661,12 +6666,6 @@ enum skl_disp_power_wells { 
#define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16

#define GEN6_PCODE_DATA1			0x13812C



#define   GEN9_PCODE_READ_MEM_LATENCY		0x6

#define   GEN9_MEM_LATENCY_LEVEL_MASK		0xFF

#define   GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT	8

#define   GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT	16

#define   GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT	24



#define GEN6_GT_CORE_STATUS		0x138060

#define   GEN6_CORE_CPD_STATE_MASK	(7<<4)

#define   GEN6_RCn_MASK			7