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Commit 9043ae02 authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
Browse files

drm/i915: Re-order the PCU opcodes 



Let's keep that list sorted!

Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 71cd8423

drivers/gpu/drm/i915/i915_reg.h

+5 −5
Original line number Diff line number Diff line
@@ -6644,15 +6644,15 @@ enum skl_disp_power_wells { 


#define GEN6_PCODE_MAILBOX			0x138124

#define   GEN6_PCODE_READY			(1<<31)

#define   GEN6_READ_OC_PARAMS			0xc

#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8

#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9

#define	  GEN6_PCODE_WRITE_RC6VIDS		0x4

#define	  GEN6_PCODE_READ_RC6VIDS		0x5

#define   GEN6_PCODE_READ_D_COMP		0x10

#define   GEN6_PCODE_WRITE_D_COMP		0x11

#define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)

#define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)

#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8

#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9

#define   GEN6_READ_OC_PARAMS			0xc

#define   GEN6_PCODE_READ_D_COMP		0x10

#define   GEN6_PCODE_WRITE_D_COMP		0x11

#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17

#define   DISPLAY_IPS_CONTROL			0x19

#define	  HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A