Loading drivers/clk/qcom/gcc-sdm429w.c +9 −9 Original line number Diff line number Diff line Loading @@ -514,25 +514,25 @@ static struct clk_pll gpll6 = { }, }; static struct clk_regmap gpll6_out_main = { static struct clk_regmap gpll6_out_aux = { .enable_reg = 0x45000, .enable_mask = BIT(7), .hw.init = &(struct clk_init_data){ .name = "gpll6_out_main", .name = "gpll6_out_aux", .parent_names = (const char *[]){ "gpll6" }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, }; static struct clk_regmap gpll6_out_aux = { .enable_reg = 0x45000, .enable_mask = BIT(7), static struct clk_fixed_factor gpll6_out_main = { .mult = 1, .div = 1, .hw.init = &(struct clk_init_data){ .name = "gpll6_out_aux", .parent_names = (const char *[]){ "gpll6" }, .name = "gpll6_out_main", .parent_names = (const char *[]){ "gpll6_out_aux" }, .num_parents = 1, .ops = &clk_pll_vote_ops, .ops = &clk_fixed_factor_ops, }, }; Loading Loading @@ -3940,6 +3940,7 @@ static struct clk_dummy wcnss_m_clk = { struct clk_hw *gcc_sdm429w_hws[] = { [GPLL0_OUT_AUX] = &gpll0_out_aux.hw, [GPLL6_OUT_MAIN] = &gpll6_out_main.hw, }; static struct clk_regmap *gcc_sdm429w_clocks[] = { Loading Loading @@ -4020,7 +4021,6 @@ static struct clk_regmap *gcc_sdm429w_clocks[] = { [GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr, [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr, [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, [GPLL6_OUT_MAIN] = &gpll6_out_main, [GPLL6] = &gpll6.clkr, [GPLL6_OUT_AUX] = &gpll6_out_aux, [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, Loading Loading
drivers/clk/qcom/gcc-sdm429w.c +9 −9 Original line number Diff line number Diff line Loading @@ -514,25 +514,25 @@ static struct clk_pll gpll6 = { }, }; static struct clk_regmap gpll6_out_main = { static struct clk_regmap gpll6_out_aux = { .enable_reg = 0x45000, .enable_mask = BIT(7), .hw.init = &(struct clk_init_data){ .name = "gpll6_out_main", .name = "gpll6_out_aux", .parent_names = (const char *[]){ "gpll6" }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, }; static struct clk_regmap gpll6_out_aux = { .enable_reg = 0x45000, .enable_mask = BIT(7), static struct clk_fixed_factor gpll6_out_main = { .mult = 1, .div = 1, .hw.init = &(struct clk_init_data){ .name = "gpll6_out_aux", .parent_names = (const char *[]){ "gpll6" }, .name = "gpll6_out_main", .parent_names = (const char *[]){ "gpll6_out_aux" }, .num_parents = 1, .ops = &clk_pll_vote_ops, .ops = &clk_fixed_factor_ops, }, }; Loading Loading @@ -3940,6 +3940,7 @@ static struct clk_dummy wcnss_m_clk = { struct clk_hw *gcc_sdm429w_hws[] = { [GPLL0_OUT_AUX] = &gpll0_out_aux.hw, [GPLL6_OUT_MAIN] = &gpll6_out_main.hw, }; static struct clk_regmap *gcc_sdm429w_clocks[] = { Loading Loading @@ -4020,7 +4021,6 @@ static struct clk_regmap *gcc_sdm429w_clocks[] = { [GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr, [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr, [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, [GPLL6_OUT_MAIN] = &gpll6_out_main, [GPLL6] = &gpll6.clkr, [GPLL6_OUT_AUX] = &gpll6_out_aux, [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, Loading