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Commit 5d15798b authored by Shawn Guo's avatar Shawn Guo
Browse files

Merge branch 'imx/soc' into imx/dt

parents cbd54fe0 c2053895

Documentation/devicetree/bindings/arm/fsl.txt

+12 −0
Original line number Diff line number Diff line
@@ -75,6 +75,18 @@ i.MX6q generic board 
Required root node properties:

    - compatible = "fsl,imx6q";



Freescale Vybrid Platform Device Tree Bindings

----------------------------------------------



For the Vybrid SoC familiy all variants with DDR controller are supported,

which is the VF5xx and VF6xx series. Out of historical reasons, in most

places the kernel uses vf610 to refer to the whole familiy.



Required root node compatible property (one of them):

    - compatible = "fsl,vf500";

    - compatible = "fsl,vf510";

    - compatible = "fsl,vf600";

    - compatible = "fsl,vf610";



Freescale LS1021A Platform Device Tree Bindings

------------------------------------------------

arch/arm/mach-imx/Makefile

+1 −2
Original line number Diff line number Diff line
@@ -32,8 +32,7 @@ ifeq ($(CONFIG_CPU_IDLE),y) 
obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o

obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o

obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o

# i.MX6SX reuses i.MX6Q cpuidle driver

obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6q.o

obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o

endif



ifdef CONFIG_SND_IMX_SOC

arch/arm/mach-imx/clk-gate2.c

+19 −4
Original line number Diff line number Diff line
@@ -96,15 +96,30 @@ static int clk_gate2_is_enabled(struct clk_hw *hw) 
{

	struct clk_gate2 *gate = to_clk_gate2(hw);



	if (gate->share_count)

		return !!__clk_get_enable_count(hw->clk);

	else

	return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);

}



static void clk_gate2_disable_unused(struct clk_hw *hw)

{

	struct clk_gate2 *gate = to_clk_gate2(hw);

	unsigned long flags = 0;

	u32 reg;



	spin_lock_irqsave(gate->lock, flags);



	if (!gate->share_count || *gate->share_count == 0) {

		reg = readl(gate->reg);

		reg &= ~(3 << gate->bit_idx);

		writel(reg, gate->reg);

	}



	spin_unlock_irqrestore(gate->lock, flags);

}



static struct clk_ops clk_gate2_ops = {

	.enable = clk_gate2_enable,

	.disable = clk_gate2_disable,

	.disable_unused = clk_gate2_disable_unused,

	.is_enabled = clk_gate2_is_enabled,

};

arch/arm/mach-imx/clk-pllv3.c

+7 −3
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
 * @base:	 base address of PLL registers

 * @powerup_set: set POWER bit to power up the PLL

 * @div_mask:	 mask of divider bits

 * @div_shift:	 shift of divider bits

 *

 * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3

 * is actually a multiplier, and always sits at bit 0.
@@ -40,6 +41,7 @@ struct clk_pllv3 { 
	void __iomem	*base;

	bool		powerup_set;

	u32		div_mask;

	u32		div_shift;

};



#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
@@ -97,7 +99,7 @@ static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, 
					   unsigned long parent_rate)

{

	struct clk_pllv3 *pll = to_clk_pllv3(hw);

	u32 div = readl_relaxed(pll->base)  & pll->div_mask;

	u32 div = (readl_relaxed(pll->base) >> pll->div_shift)  & pll->div_mask;



	return (div == 1) ? parent_rate * 22 : parent_rate * 20;

}
@@ -125,8 +127,8 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, 
		return -EINVAL;



	val = readl_relaxed(pll->base);

	val &= ~pll->div_mask;

	val |= div;

	val &= ~(pll->div_mask << pll->div_shift);

	val |= (div << pll->div_shift);

	writel_relaxed(val, pll->base);



	return clk_pllv3_wait_lock(pll);
@@ -295,6 +297,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 
	case IMX_PLLV3_SYS:

		ops = &clk_pllv3_sys_ops;

		break;

	case IMX_PLLV3_USB_VF610:

		pll->div_shift = 1;

	case IMX_PLLV3_USB:

		ops = &clk_pllv3_ops;

		pll->powerup_set = true;

arch/arm/mach-imx/clk-vf610.c

+6 −2
Original line number Diff line number Diff line
@@ -172,11 +172,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) 


	clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1);

	clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1);

	clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll3", "pll3_bypass_src", PLL3_CTRL, 0x1);

	clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB_VF610,     "pll3", "pll3_bypass_src", PLL3_CTRL, 0x2);

	clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV,      "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f);

	clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET,    "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3);

	clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV,      "pll6", "pll6_bypass_src", PLL6_CTRL, 0x7f);

	clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7", "pll7_bypass_src", PLL7_CTRL, 0x1);

	clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB_VF610,     "pll7", "pll7_bypass_src", PLL7_CTRL, 0x2);



	clk[VF610_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", PLL1_CTRL, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);

	clk[VF610_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", PLL2_CTRL, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
@@ -267,6 +267,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) 
	clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8));

	clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9));

	clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10));

	clk[VF610_CLK_UART4] = imx_clk_gate2("uart4", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(9));

	clk[VF610_CLK_UART5] = imx_clk_gate2("uart5", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(10));



	clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6));

	clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7));
@@ -380,6 +382,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) 
	clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1));

	clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2));



	clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7));



	imx_check_clocks(clk, ARRAY_SIZE(clk));



	clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);