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Commit 5a341331 authored by Huacai Chen's avatar Huacai Chen Committed by Ralf Baechle
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MIPS: Check TLB before handle_ri_rdhwr() for Loongson-3 

Loongson-3's micro TLB (ITLB) is not strictly a subset of JTLB. That
means: when a JTLB entry is replaced by hardware, there may be an old
valid entry exists in ITLB. So, a TLB miss exception may occur while
handle_ri_rdhwr() is running because it try to access EPC's content.
However, handle_ri_rdhwr() doesn't clear EXL, which makes a TLB Refill
exception be treated as a TLB Invalid exception and tlbp may fail. In
this case, if FTLB (which is usually set-associative instead of set-
associative) is enabled, a tlbp failure will cause an invalid tlbwi,
which will hang the whole system.

This patch rename handle_ri_rdhwr_vivt to handle_ri_rdhwr_tlbp and use
it for Loongson-3. It try to solve the same problem described as below,
but more straightforwards.

https://patchwork.linux-mips.org/patch/12591/



I think Loongson-2 has the same problem, but it has no FTLB, so we just
keep it as is.

Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
Cc: Rui Wang <wangr@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J . Hill <Steven.Hill@caviumnetworks.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/15753/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 033cffee

arch/mips/kernel/genex.S

+2 −2
Original line number Diff line number Diff line
@@ -519,7 +519,7 @@ NESTED(nmi_handler, PT_SIZE, sp) 
	BUILD_HANDLER reserved reserved sti verbose	/* others */



	.align	5

	LEAF(handle_ri_rdhwr_vivt)

	LEAF(handle_ri_rdhwr_tlbp)

	.set	push

	.set	noat

	.set	noreorder
@@ -538,7 +538,7 @@ NESTED(nmi_handler, PT_SIZE, sp) 
	.set	pop

	bltz	k1, handle_ri	/* slow path */

	/* fall thru */

	END(handle_ri_rdhwr_vivt)

	END(handle_ri_rdhwr_tlbp)



	LEAF(handle_ri_rdhwr)

	.set	push

arch/mips/kernel/traps.c

+13 −4
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ extern asmlinkage void handle_dbe(void); 
extern asmlinkage void handle_sys(void);

extern asmlinkage void handle_bp(void);

extern asmlinkage void handle_ri(void);

extern asmlinkage void handle_ri_rdhwr_vivt(void);

extern asmlinkage void handle_ri_rdhwr_tlbp(void);

extern asmlinkage void handle_ri_rdhwr(void);

extern asmlinkage void handle_cpu(void);

extern asmlinkage void handle_ov(void);
@@ -2408,9 +2408,18 @@ void __init trap_init(void) 


	set_except_vector(EXCCODE_SYS, handle_sys);

	set_except_vector(EXCCODE_BP, handle_bp);

	set_except_vector(EXCCODE_RI, rdhwr_noopt ? handle_ri :

			  (cpu_has_vtag_icache ?

			   handle_ri_rdhwr_vivt : handle_ri_rdhwr));



	if (rdhwr_noopt)

		set_except_vector(EXCCODE_RI, handle_ri);

	else {

		if (cpu_has_vtag_icache)

			set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);

		else if (current_cpu_type() == CPU_LOONGSON3)

			set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);

		else

			set_except_vector(EXCCODE_RI, handle_ri_rdhwr);

	}



	set_except_vector(EXCCODE_CPU, handle_cpu);

	set_except_vector(EXCCODE_OV, handle_ov);

	set_except_vector(EXCCODE_TR, handle_tr);