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Commit 033cffee authored by Huacai Chen's avatar Huacai Chen Committed by Ralf Baechle
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MIPS: Add MIPS_CPU_FTLB for Loongson-3A R2 



Loongson-3A R2 and newer CPU have FTLB, but Config0.MT is 1, so add
MIPS_CPU_FTLB to the CPU options.

Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J . Hill <Steven.Hill@caviumnetworks.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/15752/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 6ef90877

arch/mips/kernel/cpu-probe.c

+1 −1
Original line number Diff line number Diff line
@@ -1824,7 +1824,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) 
		}



		decode_configs(c);

		c->options |= MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;

		c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;

		c->writecombine = _CACHE_UNCACHED_ACCELERATED;

		break;

	default: