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Commit 57b4f7e6 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'linux-4.5' of git://github.com/skeggsb/linux into drm-next 

- gk20a instmem fixes / improvements
- more gm10x vs gm20x differences deal with
- better support for high-frequency hdmi modes
- pstate control interfaces moved to debugfs
- support for pcie link speed changes
- misc other fixes across the board

* 'linux-4.5' of git://github.com/skeggsb/linux: (50 commits)
  drm/nouveau/pmu: prevent falcon from acking interrupts routed to the host
  drm/nouveau/perf: change pcie speed on pstate change
  drm/nouveau/perf: add fields for pci speed and width and use it for the pstates
  drm/nouveau/bios/perf: parse the pci speed from the bios for tesla and newer cards
  drm/nouveau/pci: implement pcie speed change for kepler+
  drm/nouveau/pci: implement pcie speed change for Fermi
  drm/nouveau/pci: implement pcie speed change for tesla
  drm/nouveau/pci: implement generic code for pcie speed change
  drm/nouveau/pci: add gk104 variant
  drm/nouveau/pci: add gf106 variant
  drm/nouveau/kms: take mode_config mutex in connector hotplug path
  drm/nouveau/nouveau/perfmon: add interface files for current core voltage
  drm/nouveau/sysfs: remove pstate interface
  drm/nouveau/debugfs: add copy of sysfs pstate interface ported to debugfs
  drm/nouveau/debugfs: we need a ctrl object for debugfs
  drm/nouveau/debugfs: rename functions to indicate they are used inside drm
  drm/nouveau/debugfs: add infrastructure to add files with other fops than only read
  drm/nouveau/fifo/gf100: remove references to "daemon"
  drm/nouveau/fb/nv50: remove references to "daemon"
  drm/nouveau/clk: remove references to "daemon"
  ...
parents b483666b a18c91de

drivers/gpu/drm/nouveau/Kbuild

+0 −1
Original line number Diff line number Diff line
@@ -24,7 +24,6 @@ nouveau-y += nouveau_hwmon.o 
nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o

nouveau-y += nouveau_nvif.o

nouveau-$(CONFIG_NOUVEAU_PLATFORM_DRIVER) += nouveau_platform.o

nouveau-y += nouveau_sysfs.o

nouveau-y += nouveau_usif.o # userspace <-> nvif

nouveau-y += nouveau_vga.o

drivers/gpu/drm/nouveau/include/nvif/cl0002.h

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+66 −0
Original line number Diff line number Diff line 
#ifndef __NVIF_CL0002_H__

#define __NVIF_CL0002_H__



struct nv_dma_v0 {

	__u8  version;

#define NV_DMA_V0_TARGET_VM                                                0x00

#define NV_DMA_V0_TARGET_VRAM                                              0x01

#define NV_DMA_V0_TARGET_PCI                                               0x02

#define NV_DMA_V0_TARGET_PCI_US                                            0x03

#define NV_DMA_V0_TARGET_AGP                                               0x04

	__u8  target;

#define NV_DMA_V0_ACCESS_VM                                                0x00

#define NV_DMA_V0_ACCESS_RD                                                0x01

#define NV_DMA_V0_ACCESS_WR                                                0x02

#define NV_DMA_V0_ACCESS_RDWR                 (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)

	__u8  access;

	__u8  pad03[5];

	__u64 start;

	__u64 limit;

	/* ... chipset-specific class data */

};



struct nv50_dma_v0 {

	__u8  version;

#define NV50_DMA_V0_PRIV_VM                                                0x00

#define NV50_DMA_V0_PRIV_US                                                0x01

#define NV50_DMA_V0_PRIV__S                                                0x02

	__u8  priv;

#define NV50_DMA_V0_PART_VM                                                0x00

#define NV50_DMA_V0_PART_256                                               0x01

#define NV50_DMA_V0_PART_1KB                                               0x02

	__u8  part;

#define NV50_DMA_V0_COMP_NONE                                              0x00

#define NV50_DMA_V0_COMP_1                                                 0x01

#define NV50_DMA_V0_COMP_2                                                 0x02

#define NV50_DMA_V0_COMP_VM                                                0x03

	__u8  comp;

#define NV50_DMA_V0_KIND_PITCH                                             0x00

#define NV50_DMA_V0_KIND_VM                                                0x7f

	__u8  kind;

	__u8  pad05[3];

};



struct gf100_dma_v0 {

	__u8  version;

#define GF100_DMA_V0_PRIV_VM                                               0x00

#define GF100_DMA_V0_PRIV_US                                               0x01

#define GF100_DMA_V0_PRIV__S                                               0x02

	__u8  priv;

#define GF100_DMA_V0_KIND_PITCH                                            0x00

#define GF100_DMA_V0_KIND_VM                                               0xff

	__u8  kind;

	__u8  pad03[5];

};



struct gf119_dma_v0 {

	__u8  version;

#define GF119_DMA_V0_PAGE_LP                                               0x00

#define GF119_DMA_V0_PAGE_SP                                               0x01

	__u8  page;

#define GF119_DMA_V0_KIND_PITCH                                            0x00

#define GF119_DMA_V0_KIND_VM                                               0xff

	__u8  kind;

	__u8  pad03[5];

};

#endif

drivers/gpu/drm/nouveau/include/nvif/cl0046.h

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Original line number Diff line number Diff line 
#ifndef __NVIF_CL0046_H__

#define __NVIF_CL0046_H__



#define NV04_DISP_NTFY_VBLANK                                              0x00

#define NV04_DISP_NTFY_CONN                                                0x01



struct nv04_disp_mthd_v0 {

	__u8  version;

#define NV04_DISP_SCANOUTPOS                                               0x00

	__u8  method;

	__u8  head;

	__u8  pad03[5];

};



struct nv04_disp_scanoutpos_v0 {

	__u8  version;

	__u8  pad01[7];

	__s64 time[2];

	__u16 vblanks;

	__u16 vblanke;

	__u16 vtotal;

	__u16 vline;

	__u16 hblanks;

	__u16 hblanke;

	__u16 htotal;

	__u16 hline;

};

#endif

drivers/gpu/drm/nouveau/include/nvif/cl006b.h

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+11 −0
Original line number Diff line number Diff line 
#ifndef __NVIF_CL006B_H__

#define __NVIF_CL006B_H__



struct nv03_channel_dma_v0 {

	__u8  version;

	__u8  chid;

	__u8  pad02[2];

	__u32 offset;

	__u64 pushbuf;

};

#endif

drivers/gpu/drm/nouveau/include/nvif/cl0080.h

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+45 −0
Original line number Diff line number Diff line 
#ifndef __NVIF_CL0080_H__

#define __NVIF_CL0080_H__



struct nv_device_v0 {

	__u8  version;

	__u8  pad01[7];

	__u64 device;	/* device identifier, ~0 for client default */

};



#define NV_DEVICE_V0_INFO                                                  0x00

#define NV_DEVICE_V0_TIME                                                  0x01



struct nv_device_info_v0 {

	__u8  version;

#define NV_DEVICE_INFO_V0_IGP                                              0x00

#define NV_DEVICE_INFO_V0_PCI                                              0x01

#define NV_DEVICE_INFO_V0_AGP                                              0x02

#define NV_DEVICE_INFO_V0_PCIE                                             0x03

#define NV_DEVICE_INFO_V0_SOC                                              0x04

	__u8  platform;

	__u16 chipset;	/* from NV_PMC_BOOT_0 */

	__u8  revision;	/* from NV_PMC_BOOT_0 */

#define NV_DEVICE_INFO_V0_TNT                                              0x01

#define NV_DEVICE_INFO_V0_CELSIUS                                          0x02

#define NV_DEVICE_INFO_V0_KELVIN                                           0x03

#define NV_DEVICE_INFO_V0_RANKINE                                          0x04

#define NV_DEVICE_INFO_V0_CURIE                                            0x05

#define NV_DEVICE_INFO_V0_TESLA                                            0x06

#define NV_DEVICE_INFO_V0_FERMI                                            0x07

#define NV_DEVICE_INFO_V0_KEPLER                                           0x08

#define NV_DEVICE_INFO_V0_MAXWELL                                          0x09

	__u8  family;

	__u8  pad06[2];

	__u64 ram_size;

	__u64 ram_user;

	char  chip[16];

	char  name[64];

};



struct nv_device_time_v0 {

	__u8  version;

	__u8  pad01[7];

	__u64 time;

};

#endif