Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 55cc01fb authored by Andre Przywara's avatar Andre Przywara Committed by Christoffer Dall
Browse files

KVM: arm/arm64: vgic-new: Add SGIR register handler 



Triggering an IPI via this register is v2 specific, so the
implementation lives entirely in vgic-mmio-v2.c.

Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
parent 2c234d6f

virt/kvm/arm/vgic/vgic-mmio-v2.c

+42 −1
Original line number Diff line number Diff line
@@ -64,6 +64,47 @@ static void vgic_mmio_write_v2_misc(struct kvm_vcpu *vcpu, 
	}

}



static void vgic_mmio_write_sgir(struct kvm_vcpu *source_vcpu,

				 gpa_t addr, unsigned int len,

				 unsigned long val)

{

	int nr_vcpus = atomic_read(&source_vcpu->kvm->online_vcpus);

	int intid = val & 0xf;

	int targets = (val >> 16) & 0xff;

	int mode = (val >> 24) & 0x03;

	int c;

	struct kvm_vcpu *vcpu;



	switch (mode) {

	case 0x0:		/* as specified by targets */

		break;

	case 0x1:

		targets = (1U << nr_vcpus) - 1;			/* all, ... */

		targets &= ~(1U << source_vcpu->vcpu_id);	/* but self */

		break;

	case 0x2:		/* this very vCPU only */

		targets = (1U << source_vcpu->vcpu_id);

		break;

	case 0x3:		/* reserved */

		return;

	}



	kvm_for_each_vcpu(c, vcpu, source_vcpu->kvm) {

		struct vgic_irq *irq;



		if (!(targets & (1U << c)))

			continue;



		irq = vgic_get_irq(source_vcpu->kvm, vcpu, intid);



		spin_lock(&irq->irq_lock);

		irq->pending = true;

		irq->source |= 1U << source_vcpu->vcpu_id;



		vgic_queue_irq_unlock(source_vcpu->kvm, irq);

	}

}



static unsigned long vgic_mmio_read_target(struct kvm_vcpu *vcpu,

					   gpa_t addr, unsigned int len)

{
@@ -140,7 +181,7 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { 
		vgic_mmio_read_config, vgic_mmio_write_config, 2,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_LENGTH(GIC_DIST_SOFTINT,

		vgic_mmio_read_raz, vgic_mmio_write_wi, 4,

		vgic_mmio_read_raz, vgic_mmio_write_sgir, 4,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_CLEAR,

		vgic_mmio_read_raz, vgic_mmio_write_wi, 16,