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Commit 2c234d6f authored by Andre Przywara's avatar Andre Przywara Committed by Christoffer Dall
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KVM: arm/arm64: vgic-new: Add TARGET registers handlers 



The target register handlers are v2 emulation specific, so their
implementation lives entirely in vgic-mmio-v2.c.
We copy the old VGIC behaviour of assigning an IRQ to the first VCPU
set in the target mask instead of making it possibly pending on
multiple VCPUs.

Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
parent 79717e4a

virt/kvm/arm/vgic/vgic-mmio-v2.c

+42 −1
Original line number Diff line number Diff line
@@ -64,6 +64,47 @@ static void vgic_mmio_write_v2_misc(struct kvm_vcpu *vcpu, 
	}

}



static unsigned long vgic_mmio_read_target(struct kvm_vcpu *vcpu,

					   gpa_t addr, unsigned int len)

{

	u32 intid = VGIC_ADDR_TO_INTID(addr, 8);

	int i;

	u64 val = 0;



	for (i = 0; i < len; i++) {

		struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);



		val |= (u64)irq->targets << (i * 8);

	}



	return val;

}



static void vgic_mmio_write_target(struct kvm_vcpu *vcpu,

				   gpa_t addr, unsigned int len,

				   unsigned long val)

{

	u32 intid = VGIC_ADDR_TO_INTID(addr, 8);

	int i;



	/* GICD_ITARGETSR[0-7] are read-only */

	if (intid < VGIC_NR_PRIVATE_IRQS)

		return;



	for (i = 0; i < len; i++) {

		struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid + i);

		int target;



		spin_lock(&irq->irq_lock);



		irq->targets = (val >> (i * 8)) & 0xff;

		target = irq->targets ? __ffs(irq->targets) : 0;

		irq->target_vcpu = kvm_get_vcpu(vcpu->kvm, target);



		spin_unlock(&irq->irq_lock);

	}

}



static const struct vgic_register_region vgic_v2_dist_registers[] = {

	REGISTER_DESC_WITH_LENGTH(GIC_DIST_CTRL,

		vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12,
@@ -93,7 +134,7 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { 
		vgic_mmio_read_priority, vgic_mmio_write_priority, 8,

		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_TARGET,

		vgic_mmio_read_raz, vgic_mmio_write_wi, 8,

		vgic_mmio_read_target, vgic_mmio_write_target, 8,

		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_CONFIG,

		vgic_mmio_read_config, vgic_mmio_write_config, 2,