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Commit 53d98725 authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira
Browse files

drm/i915: Unduplicate VLV signal level code 



The logic for setting signal levels is used for both HDMI and DP with
small variations. But it is similar enough to put behind a function
called from the encoders.

v2: Remove unrelated MST changes due to rebase fumble. (Jim Bride)
    Fix typo in the commit message. (Jim Bride)

v3: Really fix the typo. (Jim)

Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: default avatarJim Bride <jim.bride@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461761065-21195-8-git-send-email-ander.conselvan.de.oliveira@intel.com
parent 204970b5

drivers/gpu/drm/i915/i915_drv.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -3600,6 +3600,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder); 
void chv_phy_release_cl2_override(struct intel_encoder *encoder);

void chv_phy_release_cl2_override(struct intel_encoder *encoder);

void chv_phy_post_pll_disable(struct intel_encoder *encoder);

void chv_phy_post_pll_disable(struct intel_encoder *encoder);





void vlv_set_phy_signal_level(struct intel_encoder *encoder,

			      u32 demph_reg_value, u32 preemph_reg_value,

			      u32 uniqtranscale_reg_value, u32 tx3_demph);



int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);

int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);

int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);

int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);

drivers/gpu/drm/i915/intel_dp.c

+3 −17
Original line number Original line Diff line number Diff line
@@ -2979,16 +2979,10 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 




static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)

static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)

{

{

	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);

	struct intel_crtc *intel_crtc =

		to_intel_crtc(dport->base.base.crtc);

	unsigned long demph_reg_value, preemph_reg_value,

	unsigned long demph_reg_value, preemph_reg_value,

		uniqtranscale_reg_value;

		uniqtranscale_reg_value;

	uint8_t train_set = intel_dp->train_set[0];

	uint8_t train_set = intel_dp->train_set[0];

	enum dpio_channel port = vlv_dport_to_channel(dport);

	int pipe = intel_crtc->pipe;





	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {

	case DP_TRAIN_PRE_EMPH_LEVEL_0:

	case DP_TRAIN_PRE_EMPH_LEVEL_0:
@@ -3063,16 +3057,8 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) 
		return 0;

		return 0;

	}

	}





	mutex_lock(&dev_priv->sb_lock);

	vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);

				 uniqtranscale_reg_value, 0);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),

			 uniqtranscale_reg_value);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);

	mutex_unlock(&dev_priv->sb_lock);





	return 0;

	return 0;

}

}

drivers/gpu/drm/i915/intel_dpio_phy.c

+26 −0
Original line number Original line Diff line number Diff line
@@ -369,3 +369,29 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder) 
	 */

	 */

	chv_phy_powergate_lanes(encoder, false, 0x0);

	chv_phy_powergate_lanes(encoder, false, 0x0);

}

}



void vlv_set_phy_signal_level(struct intel_encoder *encoder,

			      u32 demph_reg_value, u32 preemph_reg_value,

			      u32 uniqtranscale_reg_value, u32 tx3_demph)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);

	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);

	enum dpio_channel port = vlv_dport_to_channel(dport);

	int pipe = intel_crtc->pipe;



	mutex_lock(&dev_priv->sb_lock);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),

			 uniqtranscale_reg_value);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);



	if (tx3_demph)

		vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);



	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);

	mutex_unlock(&dev_priv->sb_lock);

}

drivers/gpu/drm/i915/intel_hdmi.c

+4 −10
Original line number Original line Diff line number Diff line
@@ -1609,21 +1609,15 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) 
	val |= 0x001000c4;

	val |= 0x001000c4;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);





	/* HDMI 1.0V-2dB */

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);

	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);



	/* Program lane clock */

	/* Program lane clock */

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);

	mutex_unlock(&dev_priv->sb_lock);

	mutex_unlock(&dev_priv->sb_lock);





	/* HDMI 1.0V-2dB */

	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,

				 0x2b247878);



	intel_hdmi->set_infoframes(&encoder->base,

	intel_hdmi->set_infoframes(&encoder->base,

				   intel_crtc->config->has_hdmi_sink,

				   intel_crtc->config->has_hdmi_sink,

				   adjusted_mode);

				   adjusted_mode);