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Commit 204970b5 authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira
Browse files

drm/i915: Unduplicate CHV encoders' post pll disable code 



The exact same code was used by HDMI and DP encoders, so move it to
intel_dpio_phy.c.

v2: Fix typo in the commit message. (Jim Bride)
v3: Call the new function chv_phy_post_pll_disable() instead of
    chv_phy_post_disable(), as it should be called after the pll
    is disabled. (Ville)

Cc: Jim Bride <jim.bride@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: default avatarJim Bride <jim.bride@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461761065-21195-7-git-send-email-ander.conselvan.de.oliveira@intel.com
parent e7d2a717

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -3598,6 +3598,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder, 
void chv_phy_pre_pll_enable(struct intel_encoder *encoder);

void chv_phy_pre_pll_enable(struct intel_encoder *encoder);

void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);

void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);

void chv_phy_release_cl2_override(struct intel_encoder *encoder);

void chv_phy_release_cl2_override(struct intel_encoder *encoder);

void chv_phy_post_pll_disable(struct intel_encoder *encoder);





int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);

int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);

int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);

int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);

drivers/gpu/drm/i915/intel_dp.c

+1 −29
Original line number Original line Diff line number Diff line
@@ -2838,35 +2838,7 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) 




static void chv_dp_post_pll_disable(struct intel_encoder *encoder)

static void chv_dp_post_pll_disable(struct intel_encoder *encoder)

{

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	chv_phy_post_pll_disable(encoder);

	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;

	u32 val;



	mutex_lock(&dev_priv->sb_lock);



	/* disable left/right clock distribution */

	if (pipe != PIPE_B) {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);

		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);

	} else {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);

		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);

	}



	mutex_unlock(&dev_priv->sb_lock);



	/*

	 * Leave the power down bit cleared for at least one

	 * lane so that chv_powergate_phy_ch() will power

	 * on something when the channel is otherwise unused.

	 * When the port is off and the override is removed

	 * the lanes power down anyway, so otherwise it doesn't

	 * really matter what the state of power down bits is

	 * after this.

	 */

	chv_phy_powergate_lanes(encoder, false, 0x0);

}

}





/*

/*

drivers/gpu/drm/i915/intel_dpio_phy.c

+33 −0
Original line number Original line Diff line number Diff line
@@ -336,3 +336,36 @@ void chv_phy_release_cl2_override(struct intel_encoder *encoder) 
		dport->release_cl2_override = false;

		dport->release_cl2_override = false;

	}

	}

}

}



void chv_phy_post_pll_disable(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;

	u32 val;



	mutex_lock(&dev_priv->sb_lock);



	/* disable left/right clock distribution */

	if (pipe != PIPE_B) {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);

		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);

	} else {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);

		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);

	}



	mutex_unlock(&dev_priv->sb_lock);



	/*

	 * Leave the power down bit cleared for at least one

	 * lane so that chv_powergate_phy_ch() will power

	 * on something when the channel is otherwise unused.

	 * When the port is off and the override is removed

	 * the lanes power down anyway, so otherwise it doesn't

	 * really matter what the state of power down bits is

	 * after this.

	 */

	chv_phy_powergate_lanes(encoder, false, 0x0);

}

drivers/gpu/drm/i915/intel_hdmi.c

+1 −29
Original line number Original line Diff line number Diff line
@@ -1675,35 +1675,7 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 




static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)

static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)

{

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	chv_phy_post_pll_disable(encoder);

	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;

	u32 val;



	mutex_lock(&dev_priv->sb_lock);



	/* disable left/right clock distribution */

	if (pipe != PIPE_B) {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);

		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);

	} else {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);

		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);

	}



	mutex_unlock(&dev_priv->sb_lock);



	/*

	 * Leave the power down bit cleared for at least one

	 * lane so that chv_powergate_phy_ch() will power

	 * on something when the channel is otherwise unused.

	 * When the port is off and the override is removed

	 * the lanes power down anyway, so otherwise it doesn't

	 * really matter what the state of power down bits is

	 * after this.

	 */

	chv_phy_powergate_lanes(encoder, false, 0x0);

}

}





static void vlv_hdmi_post_disable(struct intel_encoder *encoder)

static void vlv_hdmi_post_disable(struct intel_encoder *encoder)