Loading Documentation/devicetree/bindings/gpio/spear_spics.txt 0 → 100644 +50 −0 Original line number Diff line number Diff line === ST Microelectronics SPEAr SPI CS Driver === SPEAr platform provides a provision to control chipselects of ARM PL022 Prime Cell spi controller through its system registers, which otherwise remains under PL022 control. If chipselect remain under PL022 control then they would be released as soon as transfer is over and TxFIFO becomes empty. This is not desired by some of the device protocols above spi which expect (multiple) transfers without releasing their chipselects. Chipselects can be controlled by software by turning them as GPIOs. SPEAr provides another interface through system registers through which software can directly control each PL022 chipselect. Hence, it is natural for SPEAr to export the control of this interface as gpio. Required properties: * compatible: should be defined as "st,spear-spics-gpio" * reg: mentioning address range of spics controller * st-spics,peripcfg-reg: peripheral configuration register offset * st-spics,sw-enable-bit: bit offset to enable sw control * st-spics,cs-value-bit: bit offset to drive chipselect low or high * st-spics,cs-enable-mask: chip select number bit mask * st-spics,cs-enable-shift: chip select number program offset * gpio-controller: Marks the device node as gpio controller * #gpio-cells: should be 1 and will mention chip select number All the above bit offsets are within peripcfg register. Example: ------- spics: spics@e0700000{ compatible = "st,spear-spics-gpio"; reg = <0xe0700000 0x1000>; st-spics,peripcfg-reg = <0x3b0>; st-spics,sw-enable-bit = <12>; st-spics,cs-value-bit = <11>; st-spics,cs-enable-mask = <3>; st-spics,cs-enable-shift = <8>; gpio-controller; #gpio-cells = <2>; }; spi0: spi@e0100000 { status = "okay"; num-cs = <3>; cs-gpios = <&gpio1 7 0>, <&spics 0>, <&spics 1>; ... } arch/arm/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -364,6 +364,7 @@ config ARCH_CNS3XXX config ARCH_CLPS711X bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" select ARCH_REQUIRE_GPIOLIB select ARCH_USES_GETTIMEOFFSET select CLKDEV_LOOKUP select COMMON_CLK Loading arch/arm/plat-spear/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -12,6 +12,7 @@ config ARCH_SPEAR13XX bool "ST SPEAr13xx with Device Tree" select ARM_GIC select CPU_V7 select GPIO_SPEAR_SPICS select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 select PINCTRL Loading drivers/gpio/Kconfig +22 −0 Original line number Diff line number Diff line Loading @@ -86,11 +86,26 @@ config GPIO_DA9052 help Say yes here to enable the GPIO driver for the DA9052 chip. config GPIO_DA9055 tristate "Dialog Semiconductor DA9055 GPIO" depends on MFD_DA9055 help Say yes here to enable the GPIO driver for the DA9055 chip. The Dialog DA9055 PMIC chip has 3 GPIO pins that can be be controller by this driver. If driver is built as a module it will be called gpio-da9055. config GPIO_MAX730X tristate comment "Memory mapped GPIO drivers:" config GPIO_CLPS711X def_bool y depends on ARCH_CLPS711X config GPIO_GENERIC_PLATFORM tristate "Generic memory-mapped GPIO controller support (MMIO platform device)" select GPIO_GENERIC Loading Loading @@ -181,6 +196,13 @@ config GPIO_PXA help Say yes here to support the PXA GPIO device config GPIO_SPEAR_SPICS bool "ST SPEAr13xx SPI Chip Select as GPIO support" depends on PLAT_SPEAR select GENERIC_IRQ_CHIP help Say yes here to support ST SPEAr SPI Chip Select as GPIO device config GPIO_STA2X11 bool "STA2x11/ConneXt GPIO support" depends on MFD_STA2X11 Loading drivers/gpio/Makefile +3 −0 Original line number Diff line number Diff line Loading @@ -16,8 +16,10 @@ obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o obj-$(CONFIG_GPIO_DA9055) += gpio-da9055.o obj-$(CONFIG_ARCH_DAVINCI) += gpio-davinci.o obj-$(CONFIG_GPIO_EM) += gpio-em.o obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o Loading Loading @@ -57,6 +59,7 @@ obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o obj-$(CONFIG_GPIO_SCH) += gpio-sch.o obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o obj-$(CONFIG_GPIO_SPEAR_SPICS) += gpio-spear-spics.o obj-$(CONFIG_GPIO_STA2X11) += gpio-sta2x11.o obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o obj-$(CONFIG_GPIO_STP_XWAY) += gpio-stp-xway.o Loading Loading
Documentation/devicetree/bindings/gpio/spear_spics.txt 0 → 100644 +50 −0 Original line number Diff line number Diff line === ST Microelectronics SPEAr SPI CS Driver === SPEAr platform provides a provision to control chipselects of ARM PL022 Prime Cell spi controller through its system registers, which otherwise remains under PL022 control. If chipselect remain under PL022 control then they would be released as soon as transfer is over and TxFIFO becomes empty. This is not desired by some of the device protocols above spi which expect (multiple) transfers without releasing their chipselects. Chipselects can be controlled by software by turning them as GPIOs. SPEAr provides another interface through system registers through which software can directly control each PL022 chipselect. Hence, it is natural for SPEAr to export the control of this interface as gpio. Required properties: * compatible: should be defined as "st,spear-spics-gpio" * reg: mentioning address range of spics controller * st-spics,peripcfg-reg: peripheral configuration register offset * st-spics,sw-enable-bit: bit offset to enable sw control * st-spics,cs-value-bit: bit offset to drive chipselect low or high * st-spics,cs-enable-mask: chip select number bit mask * st-spics,cs-enable-shift: chip select number program offset * gpio-controller: Marks the device node as gpio controller * #gpio-cells: should be 1 and will mention chip select number All the above bit offsets are within peripcfg register. Example: ------- spics: spics@e0700000{ compatible = "st,spear-spics-gpio"; reg = <0xe0700000 0x1000>; st-spics,peripcfg-reg = <0x3b0>; st-spics,sw-enable-bit = <12>; st-spics,cs-value-bit = <11>; st-spics,cs-enable-mask = <3>; st-spics,cs-enable-shift = <8>; gpio-controller; #gpio-cells = <2>; }; spi0: spi@e0100000 { status = "okay"; num-cs = <3>; cs-gpios = <&gpio1 7 0>, <&spics 0>, <&spics 1>; ... }
arch/arm/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -364,6 +364,7 @@ config ARCH_CNS3XXX config ARCH_CLPS711X bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" select ARCH_REQUIRE_GPIOLIB select ARCH_USES_GETTIMEOFFSET select CLKDEV_LOOKUP select COMMON_CLK Loading
arch/arm/plat-spear/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -12,6 +12,7 @@ config ARCH_SPEAR13XX bool "ST SPEAr13xx with Device Tree" select ARM_GIC select CPU_V7 select GPIO_SPEAR_SPICS select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 select PINCTRL Loading
drivers/gpio/Kconfig +22 −0 Original line number Diff line number Diff line Loading @@ -86,11 +86,26 @@ config GPIO_DA9052 help Say yes here to enable the GPIO driver for the DA9052 chip. config GPIO_DA9055 tristate "Dialog Semiconductor DA9055 GPIO" depends on MFD_DA9055 help Say yes here to enable the GPIO driver for the DA9055 chip. The Dialog DA9055 PMIC chip has 3 GPIO pins that can be be controller by this driver. If driver is built as a module it will be called gpio-da9055. config GPIO_MAX730X tristate comment "Memory mapped GPIO drivers:" config GPIO_CLPS711X def_bool y depends on ARCH_CLPS711X config GPIO_GENERIC_PLATFORM tristate "Generic memory-mapped GPIO controller support (MMIO platform device)" select GPIO_GENERIC Loading Loading @@ -181,6 +196,13 @@ config GPIO_PXA help Say yes here to support the PXA GPIO device config GPIO_SPEAR_SPICS bool "ST SPEAr13xx SPI Chip Select as GPIO support" depends on PLAT_SPEAR select GENERIC_IRQ_CHIP help Say yes here to support ST SPEAr SPI Chip Select as GPIO device config GPIO_STA2X11 bool "STA2x11/ConneXt GPIO support" depends on MFD_STA2X11 Loading
drivers/gpio/Makefile +3 −0 Original line number Diff line number Diff line Loading @@ -16,8 +16,10 @@ obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o obj-$(CONFIG_GPIO_DA9055) += gpio-da9055.o obj-$(CONFIG_ARCH_DAVINCI) += gpio-davinci.o obj-$(CONFIG_GPIO_EM) += gpio-em.o obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o Loading Loading @@ -57,6 +59,7 @@ obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o obj-$(CONFIG_GPIO_SCH) += gpio-sch.o obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o obj-$(CONFIG_GPIO_SPEAR_SPICS) += gpio-spear-spics.o obj-$(CONFIG_GPIO_STA2X11) += gpio-sta2x11.o obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o obj-$(CONFIG_GPIO_STP_XWAY) += gpio-stp-xway.o Loading