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Commit 5215eef3 authored by Oscar Mateo's avatar Oscar Mateo Committed by Mika Kuoppala
Browse files

drm/i915/icl: Wa_1604302699 



Disable I2M Write for performance reasons.

v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
  - Rebased
  - C, not lisp (Chris)
  - GEN7 chicken bit in the wrong side of the fence (Mika)
  - Use two spaces to align bit macros

References: HSDES#1604302699
Signed-off-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-12-git-send-email-oscar.mateo@intel.com
parent 36204d80

drivers/gpu/drm/i915/i915_reg.h

+3 −1
Original line number Diff line number Diff line
@@ -7228,6 +7228,8 @@ enum { 


#define GEN7_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB030)

#define   GEN7_WA_L3_CHICKEN_MODE		0x20000000

#define GEN10_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB114)

#define   GEN11_I2M_WRITE_DISABLE		(1 << 28)



#define GEN7_L3SQCREG4				_MMIO(0xb034)

#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)

drivers/gpu/drm/i915/intel_workarounds.c

+5 −0
Original line number Diff line number Diff line
@@ -750,6 +750,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) 
	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,

		   I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |

		   GWUNIT_CLKGATE_DIS);



	/* Wa_1604302699:icl */

	I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,

		   I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |

		   GEN11_I2M_WRITE_DISABLE);

}



void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)