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Commit 5140c27c authored by Trilok Soni's avatar Trilok Soni Committed by Gerrit - the friendly Code Review server
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arm64: errata: Enable #845719 Errataum for Kryo2xx Silver 



Errata#845719 is also applicable for Kryo2xx Silver. Enable
the appropriate entry for it with rAp4 revision.

Please note that default midr_range logic depends on the
less or greather than logic with "min" and "max" range,
assuming that rX where X will be zero only. This is not
true for all the processors and since it is 4-bit field
it can be greater than the the "max" or pY bits.

We are specifying the direct match values like
version 0xA and revision 0x4 instead here to keep the
logic consistent.

Change-Id: I16b0c2106ae649b8a23b7ebb534c967aebd72774
Signed-off-by: default avatarTrilok Soni <tsoni@codeaurora.org>
Signed-off-by: default avatarGaurav Kohli <gkohli@codeaurora.org>
[cchidipu@codeaurora.org: resolve trivial merge conflicts]
[cchidipu@codeaurora.org: Update midrs in arm64_workaround_845719_cpus]
Signed-off-by: default avatarChandra Sai Chidipudi <cchidipu@codeaurora.org>
parent 31d4a5cc

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -130,6 +130,8 @@ 
#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)

#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)

#define MIDR_KRYO2XX_GOLD \

#define MIDR_KRYO2XX_GOLD \

	MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_GOLD)

	MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_GOLD)

#define MIDR_KRYO2XX_SILVER \

	MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_SILVER)





#ifndef __ASSEMBLY__

#ifndef __ASSEMBLY__

arch/arm64/kernel/cpu_errata.c

+13 −2
Original line number Original line Diff line number Diff line
@@ -562,6 +562,18 @@ static const struct midr_range arm64_workaround_1188873_cpus[] = { 




#endif

#endif





#ifdef CONFIG_ARM64_ERRATUM_845719



static const struct midr_range arm64_workaround_845719_cpus[] = {

	/* Cortex-A53 r0p[01234] */

	MIDR_RANGE(MIDR_CORTEX_A53, 0, 0, 0, 4),

	/* Kryo2xx Silver rAp4 */

	MIDR_RANGE(MIDR_KRYO2XX_SILVER, 0xA, 0x4, 0xA, 0x4),

	{},

};



#endif



const struct arm64_cpu_capabilities arm64_errata[] = {

const struct arm64_cpu_capabilities arm64_errata[] = {

#if	defined(CONFIG_ARM64_ERRATUM_826319) || \

#if	defined(CONFIG_ARM64_ERRATUM_826319) || \

	defined(CONFIG_ARM64_ERRATUM_827319) || \

	defined(CONFIG_ARM64_ERRATUM_827319) || \
@@ -614,10 +626,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
#endif

#endif

#ifdef CONFIG_ARM64_ERRATUM_845719

#ifdef CONFIG_ARM64_ERRATUM_845719

	{

	{

	/* Cortex-A53 r0p[01234] */

		.desc = "ARM erratum 845719",

		.desc = "ARM erratum 845719",

		.capability = ARM64_WORKAROUND_845719,

		.capability = ARM64_WORKAROUND_845719,

		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),

		ERRATA_MIDR_RANGE_LIST(arm64_workaround_845719_cpus),

	},

	},

#endif

#endif

#ifdef CONFIG_CAVIUM_ERRATUM_23154

#ifdef CONFIG_CAVIUM_ERRATUM_23154