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Commit 4fa086b9 authored by Leo (Sunpeng) Li's avatar Leo (Sunpeng) Li Committed by Alex Deucher
Browse files

drm/amd/display: Roll core_stream into dc_stream 



Signed-off-by: default avatarLeo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2248eb6b

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+1 −1
Original line number Diff line number Diff line
@@ -1401,7 +1401,7 @@ static int amdgpu_notify_freesync(struct drm_device *dev, void *data, 
	num_streams = dc_get_current_stream_count(adev->dm.dc);



	for (i = 0; i < num_streams; i++) {

		const struct dc_stream *stream;

		struct dc_stream *stream;

		stream = dc_get_stream_at_index(adev->dm.dc, i);



		mod_freesync_update_state(adev->dm.freesync_module,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c

+5 −5
Original line number Diff line number Diff line
@@ -2196,7 +2196,7 @@ static bool is_scaling_state_different( 
static void remove_stream(

		struct amdgpu_device *adev,

		struct amdgpu_crtc *acrtc,

		const struct dc_stream *stream)

		struct dc_stream *stream)

{

	/* this is the update mode case */

	if (adev->dm.freesync_module)
@@ -2351,7 +2351,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, 
	uint32_t i;

	struct drm_plane *plane;

	struct drm_plane_state *old_plane_state;

	const struct dc_stream *dc_stream_attach;

	struct dc_stream *dc_stream_attach;

	struct dc_surface *dc_surfaces_constructed[MAX_SURFACES];

	struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);

	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state);
@@ -2487,7 +2487,7 @@ void amdgpu_dm_atomic_commit_tail( 
	struct drm_crtc *crtc, *pcrtc;

	struct drm_crtc_state *old_crtc_state;

	struct amdgpu_crtc *new_crtcs[MAX_STREAMS];

	const struct dc_stream *new_stream;

	struct dc_stream *new_stream = NULL;

	unsigned long flags;

	bool wait_for_vblank = true;

	struct drm_connector *connector;
@@ -2822,8 +2822,8 @@ static uint32_t add_val_sets_surface( 
static uint32_t update_in_val_sets_stream(

	struct dc_validation_set *val_sets,

	uint32_t set_count,

	const struct dc_stream *old_stream,

	const struct dc_stream *new_stream,

	struct dc_stream *old_stream,

	struct dc_stream *new_stream,

	struct drm_crtc *crtc)

{

	uint32_t i = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h

+1 −1
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ struct dm_plane_state { 


struct dm_crtc_state {

	struct drm_crtc_state base;

	const struct dc_stream *stream;

	struct dc_stream *stream;

};



#define to_dm_crtc_state(x)    container_of(x, struct dm_crtc_state, base)

drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c

+8 −8
Original line number Diff line number Diff line
@@ -2610,9 +2610,9 @@ static void populate_initial_data( 


		data->fbc_en[num_displays + 4] = false;

		data->lpt_en[num_displays + 4] = false;

		data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.h_total);

		data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.v_total);

		data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->public.timing.pix_clk_khz, 1000);

		data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);

		data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);

		data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000);

		data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.width);

		data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];

		data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.height);
@@ -2707,9 +2707,9 @@ static void populate_initial_data( 


		data->fbc_en[num_displays + 4] = false;

		data->lpt_en[num_displays + 4] = false;

		data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.h_total);

		data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.v_total);

		data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->public.timing.pix_clk_khz, 1000);

		data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);

		data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);

		data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000);

		if (pipe[i].surface) {

			data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.width);

			data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
@@ -2759,9 +2759,9 @@ static void populate_initial_data( 
				break;

			}

		} else {

			data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.h_addressable);

			data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable);

			data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];

			data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.v_addressable);

			data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_addressable);

			data->h_taps[num_displays + 4] = bw_int_to_fixed(1);

			data->v_taps[num_displays + 4] = bw_int_to_fixed(1);

			data->h_scale_ratio[num_displays + 4] = bw_int_to_fixed(1);

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

+46 −46
Original line number Diff line number Diff line
@@ -365,7 +365,7 @@ static void pipe_ctx_to_e2e_pipe_params ( 
	}





	input->dest.vactive        = pipe->stream->public.timing.v_addressable;

	input->dest.vactive        = pipe->stream->timing.v_addressable;



	input->dest.recout_width   = pipe->scl_data.recout.width;

	input->dest.recout_height  = pipe->scl_data.recout.height;
@@ -373,24 +373,24 @@ static void pipe_ctx_to_e2e_pipe_params ( 
	input->dest.full_recout_width   = pipe->scl_data.recout.width;

	input->dest.full_recout_height  = pipe->scl_data.recout.height;



	input->dest.htotal         = pipe->stream->public.timing.h_total;

	input->dest.hblank_start   = input->dest.htotal - pipe->stream->public.timing.h_front_porch;

	input->dest.htotal         = pipe->stream->timing.h_total;

	input->dest.hblank_start   = input->dest.htotal - pipe->stream->timing.h_front_porch;

	input->dest.hblank_end     = input->dest.hblank_start

			- pipe->stream->public.timing.h_addressable

			- pipe->stream->public.timing.h_border_left

			- pipe->stream->public.timing.h_border_right;

			- pipe->stream->timing.h_addressable

			- pipe->stream->timing.h_border_left

			- pipe->stream->timing.h_border_right;



	input->dest.vtotal         = pipe->stream->public.timing.v_total;

	input->dest.vblank_start   = input->dest.vtotal - pipe->stream->public.timing.v_front_porch;

	input->dest.vtotal         = pipe->stream->timing.v_total;

	input->dest.vblank_start   = input->dest.vtotal - pipe->stream->timing.v_front_porch;

	input->dest.vblank_end     = input->dest.vblank_start

			- pipe->stream->public.timing.v_addressable

			- pipe->stream->public.timing.v_border_bottom

			- pipe->stream->public.timing.v_border_top;



	input->dest.vsync_plus_back_porch = pipe->stream->public.timing.v_total

			- pipe->stream->public.timing.v_addressable

			- pipe->stream->public.timing.v_front_porch;

	input->dest.pixel_rate_mhz = pipe->stream->public.timing.pix_clk_khz/1000.0;

			- pipe->stream->timing.v_addressable

			- pipe->stream->timing.v_border_bottom

			- pipe->stream->timing.v_border_top;



	input->dest.vsync_plus_back_porch = pipe->stream->timing.v_total

			- pipe->stream->timing.v_addressable

			- pipe->stream->timing.v_front_porch;

	input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_khz/1000.0;

	input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;

	input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;

	input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
@@ -851,14 +851,14 @@ bool dcn_validate_bandwidth( 
		v->underscan_output[input_idx] = false; /* taken care of in recout already*/

		v->interlace_output[input_idx] = false;



		v->htotal[input_idx] = pipe->stream->public.timing.h_total;

		v->vtotal[input_idx] = pipe->stream->public.timing.v_total;

		v->v_sync_plus_back_porch[input_idx] = pipe->stream->public.timing.v_total

				- pipe->stream->public.timing.v_addressable

				- pipe->stream->public.timing.v_front_porch;

		v->vactive[input_idx] = pipe->stream->public.timing.v_addressable;

		v->pixel_clock[input_idx] = pipe->stream->public.timing.pix_clk_khz / 1000.0f;

		if (pipe->stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

		v->htotal[input_idx] = pipe->stream->timing.h_total;

		v->vtotal[input_idx] = pipe->stream->timing.v_total;

		v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total

				- pipe->stream->timing.v_addressable

				- pipe->stream->timing.v_front_porch;

		v->vactive[input_idx] = pipe->stream->timing.v_addressable;

		v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz / 1000.0f;

		if (pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

			v->pixel_clock[input_idx] /= 2;
@@ -867,10 +867,10 @@ bool dcn_validate_bandwidth( 
			v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;

			v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s;

			v->lb_bit_per_pixel[input_idx] = 30;

			v->viewport_width[input_idx] = pipe->stream->public.timing.h_addressable;

			v->viewport_height[input_idx] = pipe->stream->public.timing.v_addressable;

			v->scaler_rec_out_width[input_idx] = pipe->stream->public.timing.h_addressable;

			v->scaler_recout_height[input_idx] = pipe->stream->public.timing.v_addressable;

			v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;

			v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;

			v->scaler_rec_out_width[input_idx] = pipe->stream->timing.h_addressable;

			v->scaler_recout_height[input_idx] = pipe->stream->timing.v_addressable;

			v->override_hta_ps[input_idx] = 1;

			v->override_vta_ps[input_idx] = 1;

			v->override_hta_pschroma[input_idx] = 1;
@@ -995,22 +995,22 @@ bool dcn_validate_bandwidth( 
			pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx];

			pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];



			pipe->pipe_dlg_param.htotal = pipe->stream->public.timing.h_total;

			pipe->pipe_dlg_param.vtotal = pipe->stream->public.timing.v_total;

			vesa_sync_start = pipe->stream->public.timing.v_addressable +

						pipe->stream->public.timing.v_border_bottom +

						pipe->stream->public.timing.v_front_porch;

			pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;

			pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;

			vesa_sync_start = pipe->stream->timing.v_addressable +

						pipe->stream->timing.v_border_bottom +

						pipe->stream->timing.v_front_porch;



			asic_blank_end = (pipe->stream->public.timing.v_total -

			asic_blank_end = (pipe->stream->timing.v_total -

						vesa_sync_start -

						pipe->stream->public.timing.v_border_top)

			* (pipe->stream->public.timing.flags.INTERLACE ? 1 : 0);

						pipe->stream->timing.v_border_top)

			* (pipe->stream->timing.flags.INTERLACE ? 1 : 0);



			asic_blank_start = asic_blank_end +

						(pipe->stream->public.timing.v_border_top +

						pipe->stream->public.timing.v_addressable +

						pipe->stream->public.timing.v_border_bottom)

			* (pipe->stream->public.timing.flags.INTERLACE ? 1 : 0);

						(pipe->stream->timing.v_border_top +

						pipe->stream->timing.v_addressable +

						pipe->stream->timing.v_border_bottom)

			* (pipe->stream->timing.flags.INTERLACE ? 1 : 0);



			pipe->pipe_dlg_param.vblank_start = asic_blank_start;

			pipe->pipe_dlg_param.vblank_end = asic_blank_end;
@@ -1019,13 +1019,13 @@ bool dcn_validate_bandwidth( 
				struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;



				if (v->dpp_per_plane[input_idx] == 2 ||

					((pipe->stream->public.view_format ==

					((pipe->stream->view_format ==

					  VIEW_3D_FORMAT_SIDE_BY_SIDE ||

					  pipe->stream->public.view_format ==

					  pipe->stream->view_format ==

					  VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&

					(pipe->stream->public.timing.timing_3d_format ==

					(pipe->stream->timing.timing_3d_format ==

					 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||

					 pipe->stream->public.timing.timing_3d_format ==

					 pipe->stream->timing.timing_3d_format ==

					 TIMING_3D_FORMAT_SIDE_BY_SIDE))) {

					if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) {

						/* update previously split pipe */
@@ -1034,8 +1034,8 @@ bool dcn_validate_bandwidth( 
						hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx];

						hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];



						hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->public.timing.h_total;

						hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->public.timing.v_total;

						hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;

						hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;

						hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start;

						hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;

					} else {