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Commit 2248eb6b authored by Tony Cheng's avatar Tony Cheng Committed by Alex Deucher
Browse files

drm/amd/display: log HUBP using DTN logging 



also simplify DTN INFO.  all we need is a way to have DC log register states
some where we can compare with golden.  going through connectivity is overkill.

Signed-off-by: default avatarTony Cheng <tony.cheng@amd.com>
Reviewed-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d1f69890

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

+9 −0
Original line number Diff line number Diff line
@@ -327,6 +327,15 @@ bool dm_helpers_dc_conn_log(struct dc_context *ctx, struct log_entry *entry, enu 
	return true;

}



void dm_dtn_log_begin(struct dc_context *ctx)

{}



void dm_dtn_log_append_v(struct dc_context *ctx,

		const char *pMsg, ...)

{}



void dm_dtn_log_end(struct dc_context *ctx)

{}



bool dm_helpers_dp_mst_start_top_mgr(

		struct dc_context *ctx,

drivers/gpu/drm/amd/display/dc/basics/log_helpers.c

+0 −28
Original line number Diff line number Diff line
@@ -100,31 +100,3 @@ void dc_conn_log(struct dc_context *ctx, 


	va_end(args);

}
 


void dc_raw_log(struct dc_context *ctx,

		enum dc_log_type event,

		const char *msg,

		...)

{

	va_list args;

	struct log_entry entry = { 0 };



	dm_logger_open(ctx->logger, &entry, event);



	va_start(args, msg);

	entry.buf_offset += dm_log_to_buffer(

		&entry.buf[entry.buf_offset],

		LOG_MAX_LINE_SIZE - entry.buf_offset,

		msg, args);



	if (entry.buf[strlen(entry.buf) - 1] == '\n') {

		entry.buf[strlen(entry.buf) - 1] = '\0';

		entry.buf_offset--;

	}



	dm_logger_append(&entry, "^\n");

	dm_helpers_dc_conn_log(ctx, &entry, event);

	dm_logger_close(&entry);



	va_end(args);

}

drivers/gpu/drm/amd/display/dc/basics/logger.c

+1 −2
Original line number Diff line number Diff line
@@ -428,7 +428,6 @@ void dm_logger_open( 


	logger->open_count++;



	if (log_type != LOG_DTN)

	log_heading(entry);

}

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+46 −7
Original line number Diff line number Diff line
@@ -31,9 +31,9 @@ 
#include "dce110/dce110_hw_sequencer.h"

#include "dce/dce_hwseq.h"

#include "abm.h"

#include "dcn10/dcn10_mem_input.h"

#include "dcn10/dcn10_dpp.h"

#include "dcn10/dcn10_mpc.h"

#include "mem_input.h"

#include "timing_generator.h"

#include "opp.h"

#include "ipp.h"
@@ -2402,22 +2402,61 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) 
	return;

}



static void dcn10_log_hw_state(struct core_dc *dc)



static void log_mpc_crc(struct core_dc *dc)

{

	struct dc_context *dc_ctx = dc->ctx;

	struct dce_hwseq *hws = dc->hwseq;



	DTN_INFO("Hello World");



	if (REG(MPC_CRC_RESULT_GB))

		DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",

		REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));

	if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))

		DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",

		REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));

	/* todo: add meaningful register reads and print out HW state

	 *

	 */

}



static void dcn10_log_hw_state(struct core_dc *dc)

{

	struct dc_context *dc_ctx = dc->ctx;

	struct resource_pool *pool = dc->res_pool;

	int i;



	DTN_INFO_BEGIN();



	DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t rotation \t"

			"mirror \t  sw_mode \t dcc_en \t blank_en \t ttu_dis \t"

			"min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");



	for (i = 0; i < pool->pipe_count; i++) {

		struct mem_input *mi = pool->mis[i];

		struct dcn_hubp_state s;



		dcn10_mem_input_read_state(TO_DCN10_MEM_INPUT(mi), &s);



		DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t %xh \t %xh \t "

				"%d \t %d \t %d \t %d \t"

				"%d \t %d \t %d \n",

				i,

				s.pixel_format,

				s.inuse_addr_hi,

				s.viewport_width,

				s.viewport_height,

				s.rotation_angle,

				s.h_mirror_en,

				s.sw_mode,

				s.dcc_en,

				s.blank_en,

				s.ttu_disable,

				s.min_ttu_vblank,

				s.qos_level_low_wm,

				s.qos_level_high_wm);

	}

	DTN_INFO("\n");



	log_mpc_crc(dc);



	DTN_INFO_END();

}



static void dcn10_wait_for_mpcc_disconnect(

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c

+34 −0
Original line number Diff line number Diff line
@@ -804,6 +804,40 @@ static void min_set_viewport( 
                       PRI_VIEWPORT_Y_START_C, viewport_c->y);

}



void dcn10_mem_input_read_state(struct dcn10_mem_input *mi,

		struct dcn_hubp_state *s)

{

	REG_GET(DCSURF_SURFACE_CONFIG,

			SURFACE_PIXEL_FORMAT, &s->pixel_format);



	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,

			SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);



	REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,

			PRI_VIEWPORT_WIDTH, &s->viewport_width,

			PRI_VIEWPORT_HEIGHT, &s->viewport_height);



	REG_GET_2(DCSURF_SURFACE_CONFIG,

			ROTATION_ANGLE, &s->rotation_angle,

			H_MIRROR_EN, &s->h_mirror_en);



	REG_GET(DCSURF_TILING_CONFIG,

			SW_MODE, &s->sw_mode);



	REG_GET(DCSURF_SURFACE_CONTROL,

			PRIMARY_SURFACE_DCC_EN, &s->dcc_en);



	REG_GET_2(DCHUBP_CNTL,

			HUBP_BLANK_EN, &s->blank_en,

			HUBP_TTU_DISABLE, &s->ttu_disable);



	REG_GET(DCN_GLOBAL_TTU_CNTL,

			MIN_TTU_VBLANK, &s->min_ttu_vblank);



	REG_GET_2(DCN_TTU_QOS_WM,

			QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,

			QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);

}



static struct mem_input_funcs dcn10_mem_input_funcs = {

	.mem_input_program_display_marks = min10_program_display_marks,