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Commit 4f3a8bc7 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
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drm/i915: rename some HDMI bit definitions 



Bits used only on HDMI mode now have HDMI_ prefix instead of SDVO_.
The COLOR_FORMAT bits now have prefixes (and the 12bpc bit is for HDMI
only).

Notice that this patch uncovers a bug on the SDVO code: the
COLOR_RANGE_16_235 bit can only be used if the port is in TMDS mode,
not SDVO mode. This will have to be fixed in a later patch.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent dc0fa718

drivers/gpu/drm/i915/i915_reg.h

+3 −3
Original line number Diff line number Diff line
@@ -1718,19 +1718,19 @@ 
#define   SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)



/* Gen 4 SDVO/HDMI bits: */

#define   COLOR_FORMAT_8bpc			(0 << 26)

#define   SDVO_COLOR_FORMAT_8bpc		(0 << 26)

#define   SDVO_ENCODING_SDVO			(0 << 10)

#define   SDVO_ENCODING_HDMI			(2 << 10)

#define   HDMI_MODE_SELECT_HDMI			(1 << 9) /* HDMI only */

#define   HDMI_MODE_SELECT_DVI			(0 << 9) /* HDMI only */

#define   SDVO_COLOR_RANGE_16_235		(1 << 8) /* HDMI only */

#define   HDMI_COLOR_RANGE_16_235		(1 << 8) /* HDMI only */

#define   SDVO_AUDIO_ENABLE			(1 << 6)

/* VSYNC/HSYNC bits new with 965, default is to be set */

#define   SDVO_VSYNC_ACTIVE_HIGH		(1 << 4)

#define   SDVO_HSYNC_ACTIVE_HIGH		(1 << 3)



/* Gen 5 (IBX) SDVO/HDMI bits: */

#define   COLOR_FORMAT_12bpc			(3 << 26) /* HDMI only */

#define   HDMI_COLOR_FORMAT_12bpc		(3 << 26) /* HDMI only */

#define   SDVOB_HOTPLUG_ENABLE			(1 << 23) /* SDVO only */



/* Gen 6 (CPT) SDVO/HDMI bits: */

drivers/gpu/drm/i915/intel_hdmi.c

+4 −4
Original line number Diff line number Diff line
@@ -609,9 +609,9 @@ static void intel_hdmi_mode_set(struct drm_encoder *encoder, 
		hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;



	if (intel_crtc->bpp > 24)

		hdmi_val |= COLOR_FORMAT_12bpc;

		hdmi_val |= HDMI_COLOR_FORMAT_12bpc;

	else

		hdmi_val |= COLOR_FORMAT_8bpc;

		hdmi_val |= SDVO_COLOR_FORMAT_8bpc;



	/* Required on CPT */

	if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
@@ -778,7 +778,7 @@ bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, 
		/* See CEA-861-E - 5.1 Default Encoding Parameters */

		if (intel_hdmi->has_hdmi_sink &&

		    drm_mode_cea_vic(adjusted_mode) > 1)

			intel_hdmi->color_range = SDVO_COLOR_RANGE_16_235;

			intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;

		else

			intel_hdmi->color_range = 0;

	}
@@ -941,7 +941,7 @@ intel_hdmi_set_property(struct drm_connector *connector, 
			break;

		case INTEL_BROADCAST_RGB_LIMITED:

			intel_hdmi->color_range_auto = false;

			intel_hdmi->color_range = SDVO_COLOR_RANGE_16_235;

			intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;

			break;

		default:

			return -EINVAL;

drivers/gpu/drm/i915/intel_sdvo.c

+6 −2
Original line number Diff line number Diff line
@@ -1076,9 +1076,11 @@ static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, 


	if (intel_sdvo->color_range_auto) {

		/* See CEA-861-E - 5.1 Default Encoding Parameters */

		/* FIXME: This bit is only valid when using TMDS encoding and 8

		 * bit per color mode. */

		if (intel_sdvo->has_hdmi_monitor &&

		    drm_mode_cea_vic(adjusted_mode) > 1)

			intel_sdvo->color_range = SDVO_COLOR_RANGE_16_235;

			intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;

		else

			intel_sdvo->color_range = 0;

	}
@@ -1926,7 +1928,9 @@ intel_sdvo_set_property(struct drm_connector *connector, 
			break;

		case INTEL_BROADCAST_RGB_LIMITED:

			intel_sdvo->color_range_auto = false;

			intel_sdvo->color_range = SDVO_COLOR_RANGE_16_235;

			/* FIXME: this bit is only valid when using TMDS

			 * encoding and 8 bit per color mode. */

			intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;

			break;

		default:

			return -EINVAL;