Loading arch/mips/math-emu/cp1emu.c +24 −24 Original line number Diff line number Diff line Loading @@ -70,7 +70,7 @@ static int fpux_emu(struct pt_regs *, /* Further private data for which no space exists in mips_fpu_soft_struct */ struct mips_fpu_emulator_private fpuemuprivate; struct mips_fpu_emulator_stats fpuemustats; /* Control registers */ Loading Loading @@ -210,7 +210,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) unsigned int cond; if (get_user(ir, (mips_instruction *) xcp->cp0_epc)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } Loading Loading @@ -241,7 +241,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) return SIGILL; } if (get_user(ir, (mips_instruction *) emulpc)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } /* __compute_return_epc() will have updated cp0_epc */ Loading @@ -254,7 +254,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) } emul: fpuemuprivate.stats.emulated++; fpuemustats.emulated++; switch (MIPSInst_OPCODE(ir)) { #ifndef SINGLE_ONLY_FPU case ldc1_op:{ Loading @@ -262,9 +262,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) MIPSInst_SIMM(ir)); u64 val; fpuemuprivate.stats.loads++; fpuemustats.loads++; if (get_user(val, va)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } DITOREG(val, MIPSInst_RT(ir)); Loading @@ -276,10 +276,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) MIPSInst_SIMM(ir)); u64 val; fpuemuprivate.stats.stores++; fpuemustats.stores++; DIFROMREG(val, MIPSInst_RT(ir)); if (put_user(val, va)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } break; Loading @@ -291,9 +291,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) MIPSInst_SIMM(ir)); u32 val; fpuemuprivate.stats.loads++; fpuemustats.loads++; if (get_user(val, va)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } #ifdef SINGLE_ONLY_FPU Loading @@ -311,7 +311,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) MIPSInst_SIMM(ir)); u32 val; fpuemuprivate.stats.stores++; fpuemustats.stores++; #ifdef SINGLE_ONLY_FPU if (MIPSInst_RT(ir) & 1) { /* illegal register in single-float mode */ Loading @@ -320,7 +320,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) #endif SIFROMREG(val, MIPSInst_RT(ir)); if (put_user(val, va)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } break; Loading Loading @@ -460,7 +460,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) if (get_user(ir, (mips_instruction *) (void *) xcp->cp0_epc)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } Loading Loading @@ -626,7 +626,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, { unsigned rcsr = 0; /* resulting csr */ fpuemuprivate.stats.cp1xops++; fpuemustats.cp1xops++; switch (MIPSInst_FMA_FFMT(ir)) { case s_fmt:{ /* 0 */ Loading @@ -641,9 +641,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, va = (void *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); fpuemuprivate.stats.loads++; fpuemustats.loads++; if (get_user(val, va)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } #ifdef SINGLE_ONLY_FPU Loading @@ -661,7 +661,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, va = (void *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); fpuemuprivate.stats.stores++; fpuemustats.stores++; #ifdef SINGLE_ONLY_FPU if (MIPSInst_FS(ir) & 1) { /* illegal register in single-float Loading @@ -673,7 +673,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, SIFROMREG(val, MIPSInst_FS(ir)); if (put_user(val, va)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } break; Loading Loading @@ -735,9 +735,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, va = (void *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); fpuemuprivate.stats.loads++; fpuemustats.loads++; if (get_user(val, va)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } DITOREG(val, MIPSInst_FD(ir)); Loading @@ -747,10 +747,10 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, va = (void *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); fpuemuprivate.stats.stores++; fpuemustats.stores++; DIFROMREG(val, MIPSInst_FS(ir)); if (put_user(val, va)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } break; Loading Loading @@ -818,7 +818,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, #endif } rv; /* resulting value */ fpuemuprivate.stats.cp1ops++; fpuemustats.cp1ops++; switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { case s_fmt:{ /* 0 */ union { Loading Loading @@ -1299,7 +1299,7 @@ int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp, prevepc = xcp->cp0_epc; if (get_user(insn, (mips_instruction *) xcp->cp0_epc)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } if (insn == 0) Loading arch/mips/math-emu/dsemul.c +2 −2 Original line number Diff line number Diff line Loading @@ -101,7 +101,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) err |= __put_user(cpc, &fr->epc); if (unlikely(err)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } Loading Loading @@ -138,7 +138,7 @@ int do_dsemulret(struct pt_regs *xcp) err |= __get_user(cookie, &fr->cookie); if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return 0; } Loading include/asm-mips/fpu_emulator.h +8 −10 Original line number Diff line number Diff line Loading @@ -23,17 +23,15 @@ #ifndef _ASM_FPU_EMULATOR_H #define _ASM_FPU_EMULATOR_H struct mips_fpu_emulator_private { struct { struct mips_fpu_emulator_stats { unsigned int emulated; unsigned int loads; unsigned int stores; unsigned int cp1ops; unsigned int cp1xops; unsigned int errors; } stats; }; extern struct mips_fpu_emulator_private fpuemuprivate; extern struct mips_fpu_emulator_stats fpuemustats; #endif /* _ASM_FPU_EMULATOR_H */ Loading
arch/mips/math-emu/cp1emu.c +24 −24 Original line number Diff line number Diff line Loading @@ -70,7 +70,7 @@ static int fpux_emu(struct pt_regs *, /* Further private data for which no space exists in mips_fpu_soft_struct */ struct mips_fpu_emulator_private fpuemuprivate; struct mips_fpu_emulator_stats fpuemustats; /* Control registers */ Loading Loading @@ -210,7 +210,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) unsigned int cond; if (get_user(ir, (mips_instruction *) xcp->cp0_epc)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } Loading Loading @@ -241,7 +241,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) return SIGILL; } if (get_user(ir, (mips_instruction *) emulpc)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } /* __compute_return_epc() will have updated cp0_epc */ Loading @@ -254,7 +254,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) } emul: fpuemuprivate.stats.emulated++; fpuemustats.emulated++; switch (MIPSInst_OPCODE(ir)) { #ifndef SINGLE_ONLY_FPU case ldc1_op:{ Loading @@ -262,9 +262,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) MIPSInst_SIMM(ir)); u64 val; fpuemuprivate.stats.loads++; fpuemustats.loads++; if (get_user(val, va)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } DITOREG(val, MIPSInst_RT(ir)); Loading @@ -276,10 +276,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) MIPSInst_SIMM(ir)); u64 val; fpuemuprivate.stats.stores++; fpuemustats.stores++; DIFROMREG(val, MIPSInst_RT(ir)); if (put_user(val, va)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } break; Loading @@ -291,9 +291,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) MIPSInst_SIMM(ir)); u32 val; fpuemuprivate.stats.loads++; fpuemustats.loads++; if (get_user(val, va)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } #ifdef SINGLE_ONLY_FPU Loading @@ -311,7 +311,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) MIPSInst_SIMM(ir)); u32 val; fpuemuprivate.stats.stores++; fpuemustats.stores++; #ifdef SINGLE_ONLY_FPU if (MIPSInst_RT(ir) & 1) { /* illegal register in single-float mode */ Loading @@ -320,7 +320,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) #endif SIFROMREG(val, MIPSInst_RT(ir)); if (put_user(val, va)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } break; Loading Loading @@ -460,7 +460,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) if (get_user(ir, (mips_instruction *) (void *) xcp->cp0_epc)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } Loading Loading @@ -626,7 +626,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, { unsigned rcsr = 0; /* resulting csr */ fpuemuprivate.stats.cp1xops++; fpuemustats.cp1xops++; switch (MIPSInst_FMA_FFMT(ir)) { case s_fmt:{ /* 0 */ Loading @@ -641,9 +641,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, va = (void *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); fpuemuprivate.stats.loads++; fpuemustats.loads++; if (get_user(val, va)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } #ifdef SINGLE_ONLY_FPU Loading @@ -661,7 +661,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, va = (void *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); fpuemuprivate.stats.stores++; fpuemustats.stores++; #ifdef SINGLE_ONLY_FPU if (MIPSInst_FS(ir) & 1) { /* illegal register in single-float Loading @@ -673,7 +673,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, SIFROMREG(val, MIPSInst_FS(ir)); if (put_user(val, va)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } break; Loading Loading @@ -735,9 +735,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, va = (void *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); fpuemuprivate.stats.loads++; fpuemustats.loads++; if (get_user(val, va)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } DITOREG(val, MIPSInst_FD(ir)); Loading @@ -747,10 +747,10 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, va = (void *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); fpuemuprivate.stats.stores++; fpuemustats.stores++; DIFROMREG(val, MIPSInst_FS(ir)); if (put_user(val, va)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } break; Loading Loading @@ -818,7 +818,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, #endif } rv; /* resulting value */ fpuemuprivate.stats.cp1ops++; fpuemustats.cp1ops++; switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { case s_fmt:{ /* 0 */ union { Loading Loading @@ -1299,7 +1299,7 @@ int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp, prevepc = xcp->cp0_epc; if (get_user(insn, (mips_instruction *) xcp->cp0_epc)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } if (insn == 0) Loading
arch/mips/math-emu/dsemul.c +2 −2 Original line number Diff line number Diff line Loading @@ -101,7 +101,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) err |= __put_user(cpc, &fr->epc); if (unlikely(err)) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return SIGBUS; } Loading Loading @@ -138,7 +138,7 @@ int do_dsemulret(struct pt_regs *xcp) err |= __get_user(cookie, &fr->cookie); if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) { fpuemuprivate.stats.errors++; fpuemustats.errors++; return 0; } Loading
include/asm-mips/fpu_emulator.h +8 −10 Original line number Diff line number Diff line Loading @@ -23,17 +23,15 @@ #ifndef _ASM_FPU_EMULATOR_H #define _ASM_FPU_EMULATOR_H struct mips_fpu_emulator_private { struct { struct mips_fpu_emulator_stats { unsigned int emulated; unsigned int loads; unsigned int stores; unsigned int cp1ops; unsigned int cp1xops; unsigned int errors; } stats; }; extern struct mips_fpu_emulator_private fpuemuprivate; extern struct mips_fpu_emulator_stats fpuemustats; #endif /* _ASM_FPU_EMULATOR_H */