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Commit 433bcf67 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'xtensa-20180820' of git://github.com/jcmvbkbc/linux-xtensa 

Pull Xtensa updates from Max Filippov:

 - switch xtensa arch to the generic noncoherent direct mapping
   operations

 - add support for DMA_ATTR_NO_KERNEL_MAPPING attribute

 - clean up users of platform/hardware.h in generic Xtensa code

 - fix assembly cache maintenance code for long cache lines

 - rework noMMU cache attributes initialization

 - add big-endian HiFi2 test_kc705_be CPU variant

* tag 'xtensa-20180820' of git://github.com/jcmvbkbc/linux-xtensa:
  xtensa: add test_kc705_be variant
  xtensa: clean up boot-elf/bootstrap.S
  xtensa: make bootparam parsing optional
  xtensa: drop variant IRQ support
  xtensa: drop unneeded platform/hardware.h headers
  xtensa: move PLATFORM_NR_IRQS to Kconfig
  xtensa: rework {CONFIG,PLATFORM}_DEFAULT_MEM_START
  xtensa: drop unused {CONFIG,PLATFORM}_DEFAULT_MEM_SIZE
  xtensa: rework noMMU cache attributes initialization
  xtensa: increase ranges in ___invalidate_{i,d}cache_all
  xtensa: limit offsets in __loop_cache_{all,page}
  xtensa: platform-specific handling of coherent memory
  xtensa: support DMA_ATTR_NO_KERNEL_MAPPING attribute
  xtensa: use generic dma_noncoherent_ops
parents b3721153 35d231db

arch/xtensa/Kconfig

+39 −21
Original line number Original line Diff line number Diff line
@@ -4,12 +4,15 @@ config ZONE_DMA 




config XTENSA

config XTENSA

	def_bool y

	def_bool y

	select ARCH_HAS_SYNC_DMA_FOR_CPU

	select ARCH_HAS_SYNC_DMA_FOR_DEVICE

	select ARCH_NO_COHERENT_DMA_MMAP if !MMU

	select ARCH_NO_COHERENT_DMA_MMAP if !MMU

	select ARCH_WANT_FRAME_POINTERS

	select ARCH_WANT_FRAME_POINTERS

	select ARCH_WANT_IPC_PARSE_VERSION

	select ARCH_WANT_IPC_PARSE_VERSION

	select BUILDTIME_EXTABLE_SORT

	select BUILDTIME_EXTABLE_SORT

	select CLONE_BACKWARDS

	select CLONE_BACKWARDS

	select COMMON_CLK

	select COMMON_CLK

	select DMA_NONCOHERENT_OPS

	select GENERIC_ATOMIC64

	select GENERIC_ATOMIC64

	select GENERIC_CLOCKEVENTS

	select GENERIC_CLOCKEVENTS

	select GENERIC_IRQ_SHOW

	select GENERIC_IRQ_SHOW
@@ -72,9 +75,6 @@ config TRACE_IRQFLAGS_SUPPORT 
config MMU

config MMU

	def_bool n

	def_bool n





config VARIANT_IRQ_SWITCH

	def_bool n



config HAVE_XTENSA_GPIO32

config HAVE_XTENSA_GPIO32

	def_bool n

	def_bool n
@@ -244,6 +244,23 @@ config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 




	  If in doubt, say Y.

	  If in doubt, say Y.





config MEMMAP_CACHEATTR

	hex "Cache attributes for the memory address space"

	depends on !MMU

	default 0x22222222

	help

	  These cache attributes are set up for noMMU systems. Each hex digit

	  specifies cache attributes for the corresponding 512MB memory

	  region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,

	  bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.



	  Cache attribute values are specific for the MMU type, so e.g.

	  for region protection MMUs: 2 is cache bypass, 4 is WB cached,

	  1 is WT cached, f is illegal. For ful MMU: bit 0 makes it executable,

	  bit 1 makes it writable, bits 2..3 meaning is 0: cache bypass,

	  1: WB cache, 2: WT cache, 3: special (c and e are illegal, f is

	  reserved).



config KSEG_PADDR

config KSEG_PADDR

	hex "Physical address of the KSEG mapping"

	hex "Physical address of the KSEG mapping"

	depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU

	depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU
@@ -413,6 +430,10 @@ config XTENSA_PLATFORM_XTFPGA 




endchoice

endchoice





config PLATFORM_NR_IRQS

	int

	default 3 if XTENSA_PLATFORM_XT2000

	default 0





config XTENSA_CPU_CLOCK

config XTENSA_CPU_CLOCK

	int "CPU clock rate [MHz]"

	int "CPU clock rate [MHz]"
@@ -450,6 +471,15 @@ config BUILTIN_DTB 
	string "DTB to build into the kernel image"

	string "DTB to build into the kernel image"

	depends on OF

	depends on OF





config PARSE_BOOTPARAM

	bool "Parse bootparam block"

	default y

	help

	  Parse parameters passed to the kernel from the bootloader. It may

	  be disabled if the kernel is known to run without the bootloader.



	  If unsure, say Y.



config BLK_DEV_SIMDISK

config BLK_DEV_SIMDISK

	tristate "Host file-based simulated block device support"

	tristate "Host file-based simulated block device support"

	default n

	default n
@@ -506,25 +536,13 @@ config PLATFORM_WANT_DEFAULT_MEM 
	def_bool n

	def_bool n





config DEFAULT_MEM_START

config DEFAULT_MEM_START

	hex "Physical address of the default memory area start"

	hex

	depends on PLATFORM_WANT_DEFAULT_MEM

	prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM

	default 0x00000000 if MMU

	default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM

	default 0x60000000 if !MMU

	default 0x00000000

	help

	  This is the base address of the default memory area.

	  Default memory area has platform-specific meaning, it may be used

	  for e.g. early cache initialization.



	  If unsure, leave the default value here.



config DEFAULT_MEM_SIZE

	hex "Maximal size of the default memory area"

	depends on PLATFORM_WANT_DEFAULT_MEM

	default 0x04000000

	help

	help

	  This is the size of the default memory area.

	  This is the base address used for both PAGE_OFFSET and PHYS_OFFSET

	  Default memory area has platform-specific meaning, it may be used

	  in noMMU configurations.

	  for e.g. early cache initialization.





	  If unsure, leave the default value here.

	  If unsure, leave the default value here.

arch/xtensa/boot/boot-elf/bootstrap.S

+9 −10
Original line number Original line Diff line number Diff line
@@ -15,10 +15,6 @@ 
 */

 */





#include <asm/bootparam.h>

#include <asm/bootparam.h>

#include <asm/processor.h>

#include <asm/pgtable.h>

#include <asm/page.h>

#include <asm/cacheasm.h>

#include <asm/initialize_mmu.h>

#include <asm/initialize_mmu.h>

#include <asm/vectors.h>

#include <asm/vectors.h>

#include <linux/linkage.h>

#include <linux/linkage.h>
@@ -33,16 +29,18 @@ _ResetVector: 
	.begin  no-absolute-literals

	.begin  no-absolute-literals

	.literal_position

	.literal_position





	.align 4

RomInitAddr:

#if defined(CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) && \

#if defined(CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) && \

	XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY

	XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY

	.word	CONFIG_KERNEL_LOAD_ADDRESS

	.literal RomInitAddr, CONFIG_KERNEL_LOAD_ADDRESS

#else

#else

	.word	KERNELOFFSET

	.literal RomInitAddr, KERNELOFFSET

#endif

#endif

RomBootParam:

#ifndef CONFIG_PARSE_BOOTPARAM

	.word _bootparam

	.literal RomBootParam, 0

#else

	.literal RomBootParam, _bootparam



	.align 4

_bootparam:

_bootparam:

	.short	BP_TAG_FIRST

	.short	BP_TAG_FIRST

	.short	4

	.short	4
@@ -50,6 +48,7 @@ _bootparam: 
	.short	BP_TAG_LAST

	.short	BP_TAG_LAST

	.short	0

	.short	0

	.long	0

	.long	0

#endif





	.align  4

	.align  4

_SetupMMU:

_SetupMMU:

arch/xtensa/configs/nommu_kc705_defconfig

+1 −1
Original line number Original line Diff line number Diff line
@@ -33,13 +33,13 @@ CONFIG_XTENSA_VARIANT_CUSTOM_NAME="de212" 
# CONFIG_XTENSA_VARIANT_MMU is not set

# CONFIG_XTENSA_VARIANT_MMU is not set

CONFIG_XTENSA_UNALIGNED_USER=y

CONFIG_XTENSA_UNALIGNED_USER=y

CONFIG_PREEMPT=y

CONFIG_PREEMPT=y

CONFIG_MEMMAP_CACHEATTR=0xfff2442f

# CONFIG_PCI is not set

# CONFIG_PCI is not set

CONFIG_XTENSA_PLATFORM_XTFPGA=y

CONFIG_XTENSA_PLATFORM_XTFPGA=y

CONFIG_CMDLINE_BOOL=y

CONFIG_CMDLINE_BOOL=y

CONFIG_CMDLINE="earlycon=uart8250,mmio32native,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=256M@0x60000000"

CONFIG_CMDLINE="earlycon=uart8250,mmio32native,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=256M@0x60000000"

CONFIG_USE_OF=y

CONFIG_USE_OF=y

CONFIG_BUILTIN_DTB="kc705_nommu"

CONFIG_BUILTIN_DTB="kc705_nommu"

CONFIG_DEFAULT_MEM_SIZE=0x10000000

CONFIG_BINFMT_FLAT=y

CONFIG_BINFMT_FLAT=y

CONFIG_NET=y

CONFIG_NET=y

CONFIG_PACKET=y

CONFIG_PACKET=y

arch/xtensa/include/asm/Kbuild

+1 −0
Original line number Original line Diff line number Diff line
@@ -3,6 +3,7 @@ generic-y += compat.h 
generic-y += device.h

generic-y += device.h

generic-y += div64.h

generic-y += div64.h

generic-y += dma-contiguous.h

generic-y += dma-contiguous.h

generic-y += dma-mapping.h

generic-y += emergency-restart.h

generic-y += emergency-restart.h

generic-y += exec.h

generic-y += exec.h

generic-y += extable.h

generic-y += extable.h

arch/xtensa/include/asm/cacheasm.h

+42 −27
Original line number Original line Diff line number Diff line
@@ -31,16 +31,32 @@ 
 *

 *

 */

 */





	.macro	__loop_cache_all ar at insn size line_width





	movi	\ar, 0

	.macro	__loop_cache_unroll ar at insn size line_width max_immed



	.if	(1 << (\line_width)) > (\max_immed)

	.set	_reps, 1

	.elseif	(2 << (\line_width)) > (\max_immed)

	.set	_reps, 2

	.else

	.set	_reps, 4

	.endif



	__loopi	\ar, \at, \size, (_reps << (\line_width))

	.set	_index, 0

	.rep	_reps

	\insn	\ar, _index << (\line_width)

	.set	_index, _index + 1

	.endr

	__endla	\ar, \at, _reps << (\line_width)



	.endm







	__loopi	\ar, \at, \size, (4 << (\line_width))

	.macro	__loop_cache_all ar at insn size line_width max_immed

	\insn	\ar, 0 << (\line_width)



	\insn	\ar, 1 << (\line_width)

	movi	\ar, 0

	\insn	\ar, 2 << (\line_width)

	__loop_cache_unroll \ar, \at, \insn, \size, \line_width, \max_immed

	\insn	\ar, 3 << (\line_width)

	__endla	\ar, \at, 4 << (\line_width)





	.endm

	.endm
@@ -57,14 +73,9 @@ 
	.endm

	.endm









	.macro	__loop_cache_page ar at insn line_width

	.macro	__loop_cache_page ar at insn line_width max_immed





	__loopi	\ar, \at, PAGE_SIZE, 4 << (\line_width)

	__loop_cache_unroll \ar, \at, \insn, PAGE_SIZE, \line_width, \max_immed

	\insn	\ar, 0 << (\line_width)

	\insn	\ar, 1 << (\line_width)

	\insn	\ar, 2 << (\line_width)

	\insn	\ar, 3 << (\line_width)

	__endla	\ar, \at, 4 << (\line_width)





	.endm

	.endm
@@ -72,7 +83,8 @@ 
	.macro	___unlock_dcache_all ar at

	.macro	___unlock_dcache_all ar at





#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE

#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE

	__loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH

	__loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE \

		XCHAL_DCACHE_LINEWIDTH 240

#endif

#endif





	.endm

	.endm
@@ -81,7 +93,8 @@ 
	.macro	___unlock_icache_all ar at

	.macro	___unlock_icache_all ar at





#if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE

#if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE

	__loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH

	__loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE \

		XCHAL_ICACHE_LINEWIDTH 240

#endif

#endif





	.endm

	.endm
@@ -90,7 +103,8 @@ 
	.macro	___flush_invalidate_dcache_all ar at

	.macro	___flush_invalidate_dcache_all ar at





#if XCHAL_DCACHE_SIZE

#if XCHAL_DCACHE_SIZE

	__loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH

	__loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE \

		XCHAL_DCACHE_LINEWIDTH 240

#endif

#endif





	.endm

	.endm
@@ -99,7 +113,8 @@ 
	.macro	___flush_dcache_all ar at

	.macro	___flush_dcache_all ar at





#if XCHAL_DCACHE_SIZE

#if XCHAL_DCACHE_SIZE

	__loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH

	__loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE \

		XCHAL_DCACHE_LINEWIDTH 240

#endif

#endif





	.endm

	.endm
@@ -108,8 +123,8 @@ 
	.macro	___invalidate_dcache_all ar at

	.macro	___invalidate_dcache_all ar at





#if XCHAL_DCACHE_SIZE

#if XCHAL_DCACHE_SIZE

	__loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \

	__loop_cache_all \ar \at dii XCHAL_DCACHE_SIZE \

			 XCHAL_DCACHE_LINEWIDTH

			 XCHAL_DCACHE_LINEWIDTH 1020

#endif

#endif





	.endm

	.endm
@@ -118,8 +133,8 @@ 
	.macro	___invalidate_icache_all ar at

	.macro	___invalidate_icache_all ar at





#if XCHAL_ICACHE_SIZE

#if XCHAL_ICACHE_SIZE

	__loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \

	__loop_cache_all \ar \at iii XCHAL_ICACHE_SIZE \

			 XCHAL_ICACHE_LINEWIDTH

			 XCHAL_ICACHE_LINEWIDTH 1020

#endif

#endif





	.endm

	.endm
@@ -166,7 +181,7 @@ 
	.macro	___flush_invalidate_dcache_page ar as

	.macro	___flush_invalidate_dcache_page ar as





#if XCHAL_DCACHE_SIZE

#if XCHAL_DCACHE_SIZE

	__loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH

	__loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 1020

#endif

#endif





	.endm

	.endm
@@ -175,7 +190,7 @@ 
	.macro ___flush_dcache_page ar as

	.macro ___flush_dcache_page ar as





#if XCHAL_DCACHE_SIZE

#if XCHAL_DCACHE_SIZE

	__loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH

	__loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 1020

#endif

#endif





	.endm

	.endm
@@ -184,7 +199,7 @@ 
	.macro	___invalidate_dcache_page ar as

	.macro	___invalidate_dcache_page ar as





#if XCHAL_DCACHE_SIZE

#if XCHAL_DCACHE_SIZE

	__loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH

	__loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 1020

#endif

#endif





	.endm

	.endm
@@ -193,7 +208,7 @@ 
	.macro	___invalidate_icache_page ar as

	.macro	___invalidate_icache_page ar as





#if XCHAL_ICACHE_SIZE

#if XCHAL_ICACHE_SIZE

	__loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH

	__loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 1020

#endif

#endif





	.endm
 
	.endm