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Commit 35d231db authored by Max Filippov's avatar Max Filippov
Browse files

Merge branch 'xtensa-dma-fixes' (early part) into xtensa-fixes 



This switches xtensa arch to the generic noncoherent direct mapping
operations, adds support for DMA_ATTR_NO_KERNEL_MAPPING attribute and
allows for platform-specific handling of coherent memory.

Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
parents bfd5bb6f 2cc15e80

arch/xtensa/Kconfig

+3 −0
Original line number Diff line number Diff line
@@ -4,12 +4,15 @@ config ZONE_DMA 


config XTENSA

	def_bool y

	select ARCH_HAS_SYNC_DMA_FOR_CPU

	select ARCH_HAS_SYNC_DMA_FOR_DEVICE

	select ARCH_NO_COHERENT_DMA_MMAP if !MMU

	select ARCH_WANT_FRAME_POINTERS

	select ARCH_WANT_IPC_PARSE_VERSION

	select BUILDTIME_EXTABLE_SORT

	select CLONE_BACKWARDS

	select COMMON_CLK

	select DMA_NONCOHERENT_OPS

	select GENERIC_ATOMIC64

	select GENERIC_CLOCKEVENTS

	select GENERIC_IRQ_SHOW

arch/xtensa/include/asm/Kbuild

+1 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ generic-y += compat.h 
generic-y += device.h

generic-y += div64.h

generic-y += dma-contiguous.h

generic-y += dma-mapping.h

generic-y += emergency-restart.h

generic-y += exec.h

generic-y += extable.h

arch/xtensa/include/asm/dma-mapping.h

deleted100644 → 0
+0 −26
Original line number Diff line number Diff line 
/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2003 - 2005 Tensilica Inc.

 * Copyright (C) 2015 Cadence Design Systems Inc.

 */



#ifndef _XTENSA_DMA_MAPPING_H

#define _XTENSA_DMA_MAPPING_H



#include <asm/cache.h>

#include <asm/io.h>



#include <linux/mm.h>

#include <linux/scatterlist.h>



extern const struct dma_map_ops xtensa_dma_map_ops;



static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)

{

	return &xtensa_dma_map_ops;

}



#endif	/* _XTENSA_DMA_MAPPING_H */

arch/xtensa/include/asm/kmem_layout.h

+0 −6
Original line number Diff line number Diff line
@@ -63,12 +63,6 @@ 
#error XCHAL_KSEG_PADDR is not properly aligned to XCHAL_KSEG_ALIGNMENT

#endif



#else



#define XCHAL_KSEG_CACHED_VADDR	__XTENSA_UL_CONST(0xd0000000)

#define XCHAL_KSEG_BYPASS_VADDR	__XTENSA_UL_CONST(0xd8000000)

#define XCHAL_KSEG_SIZE		__XTENSA_UL_CONST(0x08000000)



#endif



#ifndef CONFIG_KASAN

arch/xtensa/include/asm/pgtable.h

+8 −0
Original line number Diff line number Diff line
@@ -66,6 +66,7 @@ 
#define FIRST_USER_ADDRESS	0UL

#define FIRST_USER_PGD_NR	(FIRST_USER_ADDRESS >> PGDIR_SHIFT)



#ifdef CONFIG_MMU

/*

 * Virtual memory area. We keep a distance to other memory regions to be

 * on the safe side. We also use this area for cache aliasing.
@@ -80,6 +81,13 @@ 
#define TLBTEMP_SIZE		ICACHE_WAY_SIZE

#endif



#else



#define VMALLOC_START		__XTENSA_UL_CONST(0)

#define VMALLOC_END		__XTENSA_UL_CONST(0xffffffff)



#endif



/*

 * For the Xtensa architecture, the PTE layout is as follows:

 *