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Commit 419b1b7a authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira
Browse files

drm/i915: Unduplicate CHV phy-releated pre pll enabling code 



The same logic is used for DP and HDMI so move it to intel_dpio_phy.c.

v2: Rebase

Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: default avatarJim Bride <jim.bride@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461761065-21195-5-git-send-email-ander.conselvan.de.oliveira@intel.com
parent 844b2f9a

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -3595,6 +3595,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, 
			      bool uniq_trans_scale);

void chv_data_lane_soft_reset(struct intel_encoder *encoder,

			      bool reset);

void chv_phy_pre_pll_enable(struct intel_encoder *encoder);



int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);

int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);

drivers/gpu/drm/i915/intel_dp.c

+1 −82
Original line number Diff line number Diff line
@@ -131,11 +131,6 @@ static void vlv_steal_power_sequencer(struct drm_device *dev, 
				      enum pipe pipe);

static void intel_dp_unset_edid(struct intel_dp *intel_dp);



static unsigned int intel_dp_unused_lane_mask(int lane_count)

{

	return ~((1 << lane_count) - 1) & 0xf;

}



static int

intel_dp_max_link_bw(struct intel_dp  *intel_dp)

{
@@ -2915,85 +2910,9 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder) 


static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)

{

	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc =

		to_intel_crtc(encoder->base.crtc);

	enum dpio_channel ch = vlv_dport_to_channel(dport);

	enum pipe pipe = intel_crtc->pipe;

	unsigned int lane_mask =

		intel_dp_unused_lane_mask(intel_crtc->config->lane_count);

	u32 val;



	intel_dp_prepare(encoder);



	/*

	 * Must trick the second common lane into life.

	 * Otherwise we can't even access the PLL.

	 */

	if (ch == DPIO_CH0 && pipe == PIPE_B)

		dport->release_cl2_override =

			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);



	chv_phy_powergate_lanes(encoder, true, lane_mask);



	mutex_lock(&dev_priv->sb_lock);



	/* Assert data lane reset */

	chv_data_lane_soft_reset(encoder, true);



	/* program left/right clock distribution */

	if (pipe != PIPE_B) {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);

		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);

		if (ch == DPIO_CH0)

			val |= CHV_BUFLEFTENA1_FORCE;

		if (ch == DPIO_CH1)

			val |= CHV_BUFRIGHTENA1_FORCE;

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);

	} else {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);

		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);

		if (ch == DPIO_CH0)

			val |= CHV_BUFLEFTENA2_FORCE;

		if (ch == DPIO_CH1)

			val |= CHV_BUFRIGHTENA2_FORCE;

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);

	}



	/* program clock channel usage */

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));

	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;

	if (pipe != PIPE_B)

		val &= ~CHV_PCS_USEDCLKCHANNEL;

	else

		val |= CHV_PCS_USEDCLKCHANNEL;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);



	if (intel_crtc->config->lane_count > 2) {

		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));

		val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;

		if (pipe != PIPE_B)

			val &= ~CHV_PCS_USEDCLKCHANNEL;

		else

			val |= CHV_PCS_USEDCLKCHANNEL;

		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);

	}



	/*

	 * This a a bit weird since generally CL

	 * matches the pipe, but here we need to

	 * pick the CL based on the port.

	 */

	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));

	if (pipe != PIPE_B)

		val &= ~CHV_CMN_USEDCLKCHANNEL;

	else

		val |= CHV_CMN_USEDCLKCHANNEL;

	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);



	mutex_unlock(&dev_priv->sb_lock);

	chv_phy_pre_pll_enable(encoder);

}



static void chv_dp_post_pll_disable(struct intel_encoder *encoder)

drivers/gpu/drm/i915/intel_dpio_phy.c

+81 −0
Original line number Diff line number Diff line
@@ -163,3 +163,84 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder, 
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);

	}

}



void chv_phy_pre_pll_enable(struct intel_encoder *encoder)

{

	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc =

		to_intel_crtc(encoder->base.crtc);

	enum dpio_channel ch = vlv_dport_to_channel(dport);

	enum pipe pipe = intel_crtc->pipe;

	unsigned int lane_mask =

		intel_dp_unused_lane_mask(intel_crtc->config->lane_count);

	u32 val;



	/*

	 * Must trick the second common lane into life.

	 * Otherwise we can't even access the PLL.

	 */

	if (ch == DPIO_CH0 && pipe == PIPE_B)

		dport->release_cl2_override =

			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);



	chv_phy_powergate_lanes(encoder, true, lane_mask);



	mutex_lock(&dev_priv->sb_lock);



	/* Assert data lane reset */

	chv_data_lane_soft_reset(encoder, true);



	/* program left/right clock distribution */

	if (pipe != PIPE_B) {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);

		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);

		if (ch == DPIO_CH0)

			val |= CHV_BUFLEFTENA1_FORCE;

		if (ch == DPIO_CH1)

			val |= CHV_BUFRIGHTENA1_FORCE;

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);

	} else {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);

		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);

		if (ch == DPIO_CH0)

			val |= CHV_BUFLEFTENA2_FORCE;

		if (ch == DPIO_CH1)

			val |= CHV_BUFRIGHTENA2_FORCE;

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);

	}



	/* program clock channel usage */

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));

	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;

	if (pipe != PIPE_B)

		val &= ~CHV_PCS_USEDCLKCHANNEL;

	else

		val |= CHV_PCS_USEDCLKCHANNEL;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);



	if (intel_crtc->config->lane_count > 2) {

		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));

		val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;

		if (pipe != PIPE_B)

			val &= ~CHV_PCS_USEDCLKCHANNEL;

		else

			val |= CHV_PCS_USEDCLKCHANNEL;

		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);

	}



	/*

	 * This a a bit weird since generally CL

	 * matches the pipe, but here we need to

	 * pick the CL based on the port.

	 */

	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));

	if (pipe != PIPE_B)

		val &= ~CHV_CMN_USEDCLKCHANNEL;

	else

		val |= CHV_CMN_USEDCLKCHANNEL;

	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);



	mutex_unlock(&dev_priv->sb_lock);

}

drivers/gpu/drm/i915/intel_drv.h

+5 −0
Original line number Diff line number Diff line
@@ -1339,6 +1339,11 @@ bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); 
bool

intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);



static inline unsigned int intel_dp_unused_lane_mask(int lane_count)

{

	return ~((1 << lane_count) - 1) & 0xf;

}



/* intel_dp_aux_backlight.c */

int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);

drivers/gpu/drm/i915/intel_hdmi.c

+1 −73
Original line number Diff line number Diff line
@@ -1668,81 +1668,9 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 


static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)

{

	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc =

		to_intel_crtc(encoder->base.crtc);

	enum dpio_channel ch = vlv_dport_to_channel(dport);

	enum pipe pipe = intel_crtc->pipe;

	u32 val;



	intel_hdmi_prepare(encoder);



	/*

	 * Must trick the second common lane into life.

	 * Otherwise we can't even access the PLL.

	 */

	if (ch == DPIO_CH0 && pipe == PIPE_B)

		dport->release_cl2_override =

			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);



	chv_phy_powergate_lanes(encoder, true, 0x0);



	mutex_lock(&dev_priv->sb_lock);



	/* Assert data lane reset */

	chv_data_lane_soft_reset(encoder, true);



	/* program left/right clock distribution */

	if (pipe != PIPE_B) {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);

		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);

		if (ch == DPIO_CH0)

			val |= CHV_BUFLEFTENA1_FORCE;

		if (ch == DPIO_CH1)

			val |= CHV_BUFRIGHTENA1_FORCE;

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);

	} else {

		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);

		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);

		if (ch == DPIO_CH0)

			val |= CHV_BUFLEFTENA2_FORCE;

		if (ch == DPIO_CH1)

			val |= CHV_BUFRIGHTENA2_FORCE;

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);

	}



	/* program clock channel usage */

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));

	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;

	if (pipe != PIPE_B)

		val &= ~CHV_PCS_USEDCLKCHANNEL;

	else

		val |= CHV_PCS_USEDCLKCHANNEL;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));

	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;

	if (pipe != PIPE_B)

		val &= ~CHV_PCS_USEDCLKCHANNEL;

	else

		val |= CHV_PCS_USEDCLKCHANNEL;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);



	/*

	 * This a a bit weird since generally CL

	 * matches the pipe, but here we need to

	 * pick the CL based on the port.

	 */

	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));

	if (pipe != PIPE_B)

		val &= ~CHV_CMN_USEDCLKCHANNEL;

	else

		val |= CHV_CMN_USEDCLKCHANNEL;

	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);



	mutex_unlock(&dev_priv->sb_lock);

	chv_phy_pre_pll_enable(encoder);

}



static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)