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Commit 844b2f9a authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira
Browse files

drm/i915: Unduplicate chv_data_lane_soft_reset() 



The function chv_data_lane_soft_reset() was duplicated in DP and HDMI
code. Move it to intel_dpio_phy.c.

Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: default avatarJim Bride <jim.bride@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461761065-21195-4-git-send-email-ander.conselvan.de.oliveira@intel.com
parent b7fa22d8

drivers/gpu/drm/i915/i915_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -3593,6 +3593,8 @@ void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 
void chv_set_phy_signal_level(struct intel_encoder *encoder,

			      u32 deemph_reg_value, u32 margin_reg_value,

			      bool uniq_trans_scale);

void chv_data_lane_soft_reset(struct intel_encoder *encoder,

			      bool reset);



int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);

int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);

drivers/gpu/drm/i915/intel_dp.c

+0 −44
Original line number Diff line number Diff line
@@ -2460,50 +2460,6 @@ static void vlv_post_disable_dp(struct intel_encoder *encoder) 
	intel_dp_link_down(intel_dp);

}



static void chv_data_lane_soft_reset(struct intel_encoder *encoder,

				     bool reset)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));

	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

	enum pipe pipe = crtc->pipe;

	uint32_t val;



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));

	if (reset)

		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);

	else

		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);



	if (crtc->config->lane_count > 2) {

		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));

		if (reset)

			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);

		else

			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;

		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);

	}



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));

	val |= CHV_PCS_REQ_SOFTRESET_EN;

	if (reset)

		val &= ~DPIO_PCS_CLK_SOFT_RESET;

	else

		val |= DPIO_PCS_CLK_SOFT_RESET;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);



	if (crtc->config->lane_count > 2) {

		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));

		val |= CHV_PCS_REQ_SOFTRESET_EN;

		if (reset)

			val &= ~DPIO_PCS_CLK_SOFT_RESET;

		else

			val |= DPIO_PCS_CLK_SOFT_RESET;

		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);

	}

}



static void chv_post_disable_dp(struct intel_encoder *encoder)

{

	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

drivers/gpu/drm/i915/intel_dpio_phy.c

+43 −0
Original line number Diff line number Diff line
@@ -120,3 +120,46 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, 


}



void chv_data_lane_soft_reset(struct intel_encoder *encoder,

			      bool reset)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));

	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

	enum pipe pipe = crtc->pipe;

	uint32_t val;



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));

	if (reset)

		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);

	else

		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);



	if (crtc->config->lane_count > 2) {

		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));

		if (reset)

			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);

		else

			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;

		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);

	}



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));

	val |= CHV_PCS_REQ_SOFTRESET_EN;

	if (reset)

		val &= ~DPIO_PCS_CLK_SOFT_RESET;

	else

		val |= DPIO_PCS_CLK_SOFT_RESET;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);



	if (crtc->config->lane_count > 2) {

		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));

		val |= CHV_PCS_REQ_SOFTRESET_EN;

		if (reset)

			val &= ~DPIO_PCS_CLK_SOFT_RESET;

		else

			val |= DPIO_PCS_CLK_SOFT_RESET;

		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);

	}

}

drivers/gpu/drm/i915/intel_hdmi.c

+0 −44
Original line number Diff line number Diff line
@@ -1666,50 +1666,6 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 
	mutex_unlock(&dev_priv->sb_lock);

}



static void chv_data_lane_soft_reset(struct intel_encoder *encoder,

				     bool reset)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));

	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

	enum pipe pipe = crtc->pipe;

	uint32_t val;



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));

	if (reset)

		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);

	else

		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);



	if (crtc->config->lane_count > 2) {

		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));

		if (reset)

			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);

		else

			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;

		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);

	}



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));

	val |= CHV_PCS_REQ_SOFTRESET_EN;

	if (reset)

		val &= ~DPIO_PCS_CLK_SOFT_RESET;

	else

		val |= DPIO_PCS_CLK_SOFT_RESET;

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);



	if (crtc->config->lane_count > 2) {

		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));

		val |= CHV_PCS_REQ_SOFTRESET_EN;

		if (reset)

			val &= ~DPIO_PCS_CLK_SOFT_RESET;

		else

			val |= DPIO_PCS_CLK_SOFT_RESET;

		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);

	}

}



static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)

{

	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);