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Commit 3c34a845 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'imx-dt-clkdep-4.19' of... 

Merge tag 'imx-dt-clkdep-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

i.MX device tree changes with clock dependency:
 - Add clock for i.MX6UL GPIO blocks

* tag 'imx-dt-clkdep-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux

:
  ARM: dts: imx6ul: add GPIO clocks
  clk: imx6ul: remove clks_init_on array
  clk: imx6ul: add GPIO clock gates
  dt-bindings: clock: imx6ul: Do not change the clock definition order

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 88657e90 bc36b2aa

arch/arm/boot/dts/imx6ul.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -433,6 +433,7 @@ 
				reg = <0x0209c000 0x4000>;

				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX6UL_CLK_GPIO1>;

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;
@@ -446,6 +447,7 @@ 
				reg = <0x020a0000 0x4000>;

				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX6UL_CLK_GPIO2>;

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;
@@ -458,6 +460,7 @@ 
				reg = <0x020a4000 0x4000>;

				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX6UL_CLK_GPIO3>;

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;
@@ -470,6 +473,7 @@ 
				reg = <0x020a8000 0x4000>;

				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX6UL_CLK_GPIO4>;

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;
@@ -482,6 +486,7 @@ 
				reg = <0x020ac000 0x4000>;

				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX6UL_CLK_GPIO5>;

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;

drivers/clk/imx/clk-imx6ul.c

+11 −17
Original line number Diff line number Diff line
@@ -79,12 +79,6 @@ static const char *cko_sels[] = { "cko1", "cko2", }; 
static struct clk *clks[IMX6UL_CLK_END];

static struct clk_onecell_data clk_data;



static int const clks_init_on[] __initconst = {

	IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2,

	IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM,

	IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG,

};



static const struct clk_div_table clk_enet_ref_table[] = {

	{ .val = 0, .div = 20, },

	{ .val = 1, .div = 10, },
@@ -129,7 +123,6 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 
{

	struct device_node *np;

	void __iomem *base;

	int i;



	clks[IMX6UL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
@@ -336,8 +329,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 
	clks[IMX6UL_CLK_AHB]		= imx_clk_busy_divider("ahb",	    "periph",	base +  0x14, 10, 3,  base + 0x48, 1);



	/* CCGR0 */

	clks[IMX6UL_CLK_AIPSTZ1]	= imx_clk_gate2("aips_tz1",	"ahb",		base + 0x68,	0);

	clks[IMX6UL_CLK_AIPSTZ2]	= imx_clk_gate2("aips_tz2",	"ahb",		base + 0x68,	2);

	clks[IMX6UL_CLK_AIPSTZ1]	= imx_clk_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL);

	clks[IMX6UL_CLK_AIPSTZ2]	= imx_clk_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL);

	clks[IMX6UL_CLK_APBHDMA]	= imx_clk_gate2("apbh_dma",	"bch_podf",	base + 0x68,	4);

	clks[IMX6UL_CLK_ASRC_IPG]	= imx_clk_gate2_shared("asrc_ipg",	"ahb",	base + 0x68,	6, &share_count_asrc);

	clks[IMX6UL_CLK_ASRC_MEM]	= imx_clk_gate2_shared("asrc_mem",	"ahb",	base + 0x68,	6, &share_count_asrc);
@@ -360,6 +353,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 
	clks[IMX6UL_CLK_UART2_SERIAL]	= imx_clk_gate2("uart2_serial",	"uart_podf",	base + 0x68,	28);

	if (clk_on_imx6ull())

		clks[IMX6UL_CLK_AIPSTZ3]	= imx_clk_gate2("aips_tz3",	"ahb",		 base + 0x80,	18);

	clks[IMX6UL_CLK_GPIO2]		= imx_clk_gate2("gpio2",	"ipg",		base + 0x68,	30);



	/* CCGR1 */

	clks[IMX6UL_CLK_ECSPI1]		= imx_clk_gate2("ecspi1",	"ecspi_podf",	base + 0x6c,	0);
@@ -376,6 +370,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 
	clks[IMX6UL_CLK_GPT1_SERIAL]	= imx_clk_gate2("gpt1_serial",	"perclk",	base + 0x6c,	22);

	clks[IMX6UL_CLK_UART4_IPG]	= imx_clk_gate2("uart4_ipg",	"ipg",		base + 0x6c,	24);

	clks[IMX6UL_CLK_UART4_SERIAL]	= imx_clk_gate2("uart4_serial",	"uart_podf",	base + 0x6c,	24);

	clks[IMX6UL_CLK_GPIO1]		= imx_clk_gate2("gpio1",	"ipg",		base + 0x6c,	26);

	clks[IMX6UL_CLK_GPIO5]		= imx_clk_gate2("gpio5",	"ipg",		base + 0x6c,	30);



	/* CCGR2 */

	if (clk_on_imx6ull()) {
@@ -389,6 +385,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 
	clks[IMX6UL_CLK_I2C3]		= imx_clk_gate2("i2c3",		"perclk",	base + 0x70,	10);

	clks[IMX6UL_CLK_OCOTP]		= imx_clk_gate2("ocotp",	"ipg",		base + 0x70,	12);

	clks[IMX6UL_CLK_IOMUXC]		= imx_clk_gate2("iomuxc",	"lcdif_podf",	base + 0x70,	14);

	clks[IMX6UL_CLK_GPIO3]		= imx_clk_gate2("gpio3",	"ipg",		base + 0x70,	26);

	clks[IMX6UL_CLK_LCDIF_APB]	= imx_clk_gate2("lcdif_apb",	"axi",		base + 0x70,	28);

	clks[IMX6UL_CLK_PXP]		= imx_clk_gate2("pxp",		"axi",		base + 0x70,	30);
@@ -405,11 +402,12 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 
	clks[IMX6UL_CLK_UART6_IPG]	= imx_clk_gate2("uart6_ipg",	"ipg",		base + 0x74,	6);

	clks[IMX6UL_CLK_UART6_SERIAL]	= imx_clk_gate2("uart6_serial",	"uart_podf",	base + 0x74,	6);

	clks[IMX6UL_CLK_LCDIF_PIX]	= imx_clk_gate2("lcdif_pix",	"lcdif_podf",	base + 0x74,	10);

	clks[IMX6UL_CLK_GPIO4]		= imx_clk_gate2("gpio4",	"ipg",		base + 0x74,	12);

	clks[IMX6UL_CLK_QSPI]		= imx_clk_gate2("qspi1",	"qspi1_podf",	base + 0x74,	14);

	clks[IMX6UL_CLK_WDOG1]		= imx_clk_gate2("wdog1",	"ipg",		base + 0x74,	16);

	clks[IMX6UL_CLK_MMDC_P0_FAST]	= imx_clk_gate("mmdc_p0_fast", "mmdc_podf", base + 0x74,	20);

	clks[IMX6UL_CLK_MMDC_P0_IPG]	= imx_clk_gate2("mmdc_p0_ipg",	"ipg",		base + 0x74,	24);

	clks[IMX6UL_CLK_AXI]		= imx_clk_gate("axi",	"axi_podf",	base + 0x74,	28);

	clks[IMX6UL_CLK_MMDC_P0_FAST]	= imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74,	20, CLK_IS_CRITICAL);

	clks[IMX6UL_CLK_MMDC_P0_IPG]	= imx_clk_gate2_flags("mmdc_p0_ipg",	"ipg",		base + 0x74,	24, CLK_IS_CRITICAL);

	clks[IMX6UL_CLK_AXI]		= imx_clk_gate_flags("axi",	"axi_podf",	base + 0x74,	28, CLK_IS_CRITICAL);



	/* CCGR4 */

	clks[IMX6UL_CLK_PER_BCH]	= imx_clk_gate2("per_bch",	"bch_podf",	base + 0x78,	12);
@@ -423,7 +421,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 
	clks[IMX6UL_CLK_GPMI_APB]	= imx_clk_gate2("gpmi_apb",	"bch_podf",	base + 0x78,	30);



	/* CCGR5 */

	clks[IMX6UL_CLK_ROM]		= imx_clk_gate2("rom",		"ahb",		base + 0x7c,	0);

	clks[IMX6UL_CLK_ROM]		= imx_clk_gate2_flags("rom",	"ahb",		base + 0x7c,	0,	CLK_IS_CRITICAL);

	clks[IMX6UL_CLK_SDMA]		= imx_clk_gate2("sdma",		"ahb",		base + 0x7c,	6);

	clks[IMX6UL_CLK_KPP]		= imx_clk_gate2("kpp",		"ipg",		base + 0x7c,	8);

	clks[IMX6UL_CLK_WDOG2]		= imx_clk_gate2("wdog2",	"ipg",		base + 0x7c,	10);
@@ -497,10 +495,6 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 
	clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000);

	clk_set_rate(clks[IMX6UL_CLK_CSI], 24000000);



	/* keep all the clks on just for bringup */

	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)

		clk_prepare_enable(clks[clks_init_on[i]]);



	if (clk_on_imx6ull())

		clk_prepare_enable(clks[IMX6UL_CLK_AIPSTZ3]);

include/dt-bindings/clock/imx6ul-clock.h

+25 −21
Original line number Diff line number Diff line
@@ -235,27 +235,31 @@ 
#define IMX6UL_CLK_CSI_PODF		222

#define IMX6UL_CLK_PLL3_120M		223

#define IMX6UL_CLK_KPP			224

#define IMX6UL_CLK_CKO1_SEL		225

#define IMX6UL_CLK_CKO1_PODF		226

#define IMX6UL_CLK_CKO1			227

#define IMX6UL_CLK_CKO2_SEL		228

#define IMX6UL_CLK_CKO2_PODF		229

#define IMX6UL_CLK_CKO2			230

#define IMX6UL_CLK_CKO			231

#define IMX6ULL_CLK_ESAI_PRED		225

#define IMX6ULL_CLK_ESAI_PODF		226

#define IMX6ULL_CLK_ESAI_EXTAL		227

#define IMX6ULL_CLK_ESAI_MEM		228

#define IMX6ULL_CLK_ESAI_IPG		229

#define IMX6ULL_CLK_DCP_CLK		230

#define IMX6ULL_CLK_EPDC_PRE_SEL	231

#define IMX6ULL_CLK_EPDC_SEL		232

#define IMX6ULL_CLK_EPDC_PODF		233

#define IMX6ULL_CLK_EPDC_ACLK		234

#define IMX6ULL_CLK_EPDC_PIX		235

#define IMX6ULL_CLK_ESAI_SEL		236

#define IMX6UL_CLK_CKO1_SEL		237

#define IMX6UL_CLK_CKO1_PODF		238

#define IMX6UL_CLK_CKO1			239

#define IMX6UL_CLK_CKO2_SEL		240

#define IMX6UL_CLK_CKO2_PODF		241

#define IMX6UL_CLK_CKO2			242

#define IMX6UL_CLK_CKO			243

#define IMX6UL_CLK_GPIO1		244

#define IMX6UL_CLK_GPIO2		245

#define IMX6UL_CLK_GPIO3		246

#define IMX6UL_CLK_GPIO4		247

#define IMX6UL_CLK_GPIO5		248



/* For i.MX6ULL */

#define IMX6ULL_CLK_ESAI_PRED		232

#define IMX6ULL_CLK_ESAI_PODF		233

#define IMX6ULL_CLK_ESAI_EXTAL		234

#define IMX6ULL_CLK_ESAI_MEM		235

#define IMX6ULL_CLK_ESAI_IPG		236

#define IMX6ULL_CLK_DCP_CLK		237

#define IMX6ULL_CLK_EPDC_PRE_SEL	238

#define IMX6ULL_CLK_EPDC_SEL		239

#define IMX6ULL_CLK_EPDC_PODF		240

#define IMX6ULL_CLK_EPDC_ACLK		241

#define IMX6ULL_CLK_EPDC_PIX		242

#define IMX6ULL_CLK_ESAI_SEL		243

#define IMX6UL_CLK_END			244

#define IMX6UL_CLK_END			249



#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */