Loading Documentation/devicetree/bindings/clock/ti/adpll.txt 0 → 100644 +41 −0 Original line number Diff line number Diff line Binding for Texas Instruments ADPLL clock. Binding status: Unstable - ABI compatibility may be broken in the future This binding uses the common clock binding[1]. It assumes a register-mapped ADPLL with two to three selectable input clocks and three to four children. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt Required properties: - compatible : shall be one of "ti,dm814-adpll-s-clock" or "ti,dm814-adpll-lj-clock" depending on the type of the ADPLL - #clock-cells : from common clock binding; shall be set to 1. - clocks : link phandles of parent clocks clkinp and clkinpulow, note that the adpll-s-clock also has an optional clkinphif - reg : address and length of the register set for controlling the ADPLL. Examples: adpll_mpu_ck: adpll@40 { #clock-cells = <1>; compatible = "ti,dm814-adpll-s-clock"; reg = <0x40 0x40>; clocks = <&devosc_ck &devosc_ck &devosc_ck>; clock-names = "clkinp", "clkinpulow", "clkinphif"; clock-output-names = "481c5040.adpll.dcoclkldo", "481c5040.adpll.clkout", "481c5040.adpll.clkoutx2", "481c5040.adpll.clkouthif"; }; adpll_dsp_ck: adpll@80 { #clock-cells = <1>; compatible = "ti,dm814-adpll-lj-clock"; reg = <0x80 0x30>; clocks = <&devosc_ck &devosc_ck>; clock-names = "clkinp", "clkinpulow"; clock-output-names = "481c5080.adpll.dcoclkldo", "481c5080.adpll.clkout", "481c5080.adpll.clkoutldo"; }; drivers/clk/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -203,5 +203,6 @@ source "drivers/clk/mvebu/Kconfig" source "drivers/clk/qcom/Kconfig" source "drivers/clk/samsung/Kconfig" source "drivers/clk/tegra/Kconfig" source "drivers/clk/ti/Kconfig" endmenu drivers/clk/Makefile +1 −1 Original line number Diff line number Diff line Loading @@ -77,7 +77,7 @@ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-$(CONFIG_ARCH_STI) += st/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_ARCH_OMAP2PLUS) += ti/ obj-y += ti/ obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/ obj-$(CONFIG_X86) += x86/ Loading drivers/clk/ti/Kconfig 0 → 100644 +6 −0 Original line number Diff line number Diff line config COMMON_CLK_TI_ADPLL tristate "Clock driver for dm814x ADPLL" depends on ARCH_OMAP2PLUS || COMPILE_TEST default y if SOC_TI81XX ---help--- ADPLL clock driver for the dm814x SoC using common clock framework. drivers/clk/ti/Makefile +6 −0 Original line number Diff line number Diff line ifeq ($(CONFIG_ARCH_OMAP2PLUS), y) obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o mux.o apll.o \ Loading @@ -18,3 +20,7 @@ obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o ifdef CONFIG_ATAGS obj-$(CONFIG_ARCH_OMAP3) += clk-3xxx-legacy.o endif endif # CONFIG_ARCH_OMAP2PLUS obj-$(CONFIG_COMMON_CLK_TI_ADPLL) += adpll.o Loading
Documentation/devicetree/bindings/clock/ti/adpll.txt 0 → 100644 +41 −0 Original line number Diff line number Diff line Binding for Texas Instruments ADPLL clock. Binding status: Unstable - ABI compatibility may be broken in the future This binding uses the common clock binding[1]. It assumes a register-mapped ADPLL with two to three selectable input clocks and three to four children. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt Required properties: - compatible : shall be one of "ti,dm814-adpll-s-clock" or "ti,dm814-adpll-lj-clock" depending on the type of the ADPLL - #clock-cells : from common clock binding; shall be set to 1. - clocks : link phandles of parent clocks clkinp and clkinpulow, note that the adpll-s-clock also has an optional clkinphif - reg : address and length of the register set for controlling the ADPLL. Examples: adpll_mpu_ck: adpll@40 { #clock-cells = <1>; compatible = "ti,dm814-adpll-s-clock"; reg = <0x40 0x40>; clocks = <&devosc_ck &devosc_ck &devosc_ck>; clock-names = "clkinp", "clkinpulow", "clkinphif"; clock-output-names = "481c5040.adpll.dcoclkldo", "481c5040.adpll.clkout", "481c5040.adpll.clkoutx2", "481c5040.adpll.clkouthif"; }; adpll_dsp_ck: adpll@80 { #clock-cells = <1>; compatible = "ti,dm814-adpll-lj-clock"; reg = <0x80 0x30>; clocks = <&devosc_ck &devosc_ck>; clock-names = "clkinp", "clkinpulow"; clock-output-names = "481c5080.adpll.dcoclkldo", "481c5080.adpll.clkout", "481c5080.adpll.clkoutldo"; };
drivers/clk/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -203,5 +203,6 @@ source "drivers/clk/mvebu/Kconfig" source "drivers/clk/qcom/Kconfig" source "drivers/clk/samsung/Kconfig" source "drivers/clk/tegra/Kconfig" source "drivers/clk/ti/Kconfig" endmenu
drivers/clk/Makefile +1 −1 Original line number Diff line number Diff line Loading @@ -77,7 +77,7 @@ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-$(CONFIG_ARCH_STI) += st/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_ARCH_OMAP2PLUS) += ti/ obj-y += ti/ obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/ obj-$(CONFIG_X86) += x86/ Loading
drivers/clk/ti/Kconfig 0 → 100644 +6 −0 Original line number Diff line number Diff line config COMMON_CLK_TI_ADPLL tristate "Clock driver for dm814x ADPLL" depends on ARCH_OMAP2PLUS || COMPILE_TEST default y if SOC_TI81XX ---help--- ADPLL clock driver for the dm814x SoC using common clock framework.
drivers/clk/ti/Makefile +6 −0 Original line number Diff line number Diff line ifeq ($(CONFIG_ARCH_OMAP2PLUS), y) obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o mux.o apll.o \ Loading @@ -18,3 +20,7 @@ obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o ifdef CONFIG_ATAGS obj-$(CONFIG_ARCH_OMAP3) += clk-3xxx-legacy.o endif endif # CONFIG_ARCH_OMAP2PLUS obj-$(CONFIG_COMMON_CLK_TI_ADPLL) += adpll.o