Commit 811a498e authored Feb 28, 2016 by Archit Taneja Committed by Stephen Boyd Feb 29, 2016

clk: qcom: Fix pre-divider usage for pixel RCG



The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading
its current value from the NS register.

Using the pre-divider wasn't really intended when creating these ops.
The pixel RCG was only intended to achieve fractional multiplication
provided in the pixel_table array. Leaving the pre-divider to the
existing register value results in a wrong pixel clock when the
bootloader sets up the display. This was left unidentified because
the IFC6410 Plus board on which this was verified didn't have a
bootloader that configured the display.

Don't set the RCG pre-divider in freq_tbl to the existing NS register
value. Force it to 1 and only use the M/N counter to achieve the desired
fractional multiplication.

Cc: Vinay Simha <vinaysimha@inforcecomputing.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Tested-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

parent d3622b58

drivers/clk/qcom/clk-rcg.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -638,7 +638,6 @@ static int clk_rcg_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
		return ret;

		src = ns_to_src(&rcg->s, ns);
		f.pre_div = ns_to_pre_div(&rcg->p, ns) + 1;

		for (i = 0; i < num_parents; i++) {
		if (src == rcg->s.parent_map[i].cfg) {
		@@ -647,6 +646,9 @@ static int clk_rcg_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
		}
		}

		/* bypass the pre divider */
		f.pre_div = 1;

		/* let us find appropriate m/n values for this */
		for (; frac->num; frac++) {
		request = (rate * frac->den) / frac->num;