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Commit 398a017e authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Fix HDMI 12bpc and pixel repeat clock readout for DDI platforms 



Take the HDMI 12bpc mode and pixel repeat into account when extracting
the dotclock from the hardware on DDI platforms.

Tested on HSW only.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-and-tested-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ec530829

drivers/gpu/drm/i915/intel_ddi.c

+24 −25
Original line number Original line Diff line number Diff line
@@ -1027,6 +1027,26 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, 
	return dco_freq / (p0 * p1 * p2 * 5);

	return dco_freq / (p0 * p1 * p2 * 5);

}

}





static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)

{

	int dotclock;



	if (pipe_config->has_pch_encoder)

		dotclock = intel_dotclock_calculate(pipe_config->port_clock,

						    &pipe_config->fdi_m_n);

	else if (pipe_config->has_dp_encoder)

		dotclock = intel_dotclock_calculate(pipe_config->port_clock,

						    &pipe_config->dp_m_n);

	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)

		dotclock = pipe_config->port_clock * 2 / 3;

	else

		dotclock = pipe_config->port_clock;



	if (pipe_config->pixel_multiplier)

		dotclock /= pipe_config->pixel_multiplier;



	pipe_config->base.adjusted_mode.crtc_clock = dotclock;

}





static void skl_ddi_clock_get(struct intel_encoder *encoder,

static void skl_ddi_clock_get(struct intel_encoder *encoder,

				struct intel_crtc_state *pipe_config)

				struct intel_crtc_state *pipe_config)
@@ -1073,12 +1093,7 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder, 




	pipe_config->port_clock = link_clock;

	pipe_config->port_clock = link_clock;





	if (pipe_config->has_dp_encoder)

	ddi_dotclock_get(pipe_config);

		pipe_config->base.adjusted_mode.crtc_clock =

			intel_dotclock_calculate(pipe_config->port_clock,

						 &pipe_config->dp_m_n);

	else

		pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;

}

}





static void hsw_ddi_clock_get(struct intel_encoder *encoder,

static void hsw_ddi_clock_get(struct intel_encoder *encoder,
@@ -1125,16 +1140,7 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder, 




	pipe_config->port_clock = link_clock * 2;

	pipe_config->port_clock = link_clock * 2;





	if (pipe_config->has_pch_encoder)

	ddi_dotclock_get(pipe_config);

		pipe_config->base.adjusted_mode.crtc_clock =

			intel_dotclock_calculate(pipe_config->port_clock,

						 &pipe_config->fdi_m_n);

	else if (pipe_config->has_dp_encoder)

		pipe_config->base.adjusted_mode.crtc_clock =

			intel_dotclock_calculate(pipe_config->port_clock,

						 &pipe_config->dp_m_n);

	else

		pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;

}

}





static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,

static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
@@ -1169,16 +1175,9 @@ static void bxt_ddi_clock_get(struct intel_encoder *encoder, 
	enum port port = intel_ddi_get_encoder_port(encoder);

	enum port port = intel_ddi_get_encoder_port(encoder);

	uint32_t dpll = port;

	uint32_t dpll = port;





	pipe_config->port_clock =

	pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);

		bxt_calc_pll_link(dev_priv, dpll);





	if (pipe_config->has_dp_encoder)

	ddi_dotclock_get(pipe_config);

		pipe_config->base.adjusted_mode.crtc_clock =

			intel_dotclock_calculate(pipe_config->port_clock,

							&pipe_config->dp_m_n);

	else

		pipe_config->base.adjusted_mode.crtc_clock =

							pipe_config->port_clock;

}

}





void intel_ddi_clock_get(struct intel_encoder *encoder,

void intel_ddi_clock_get(struct intel_encoder *encoder,