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Commit 375074cc authored by Andy Lutomirski's avatar Andy Lutomirski Committed by Ingo Molnar
Browse files

x86: Clean up cr4 manipulation 



CR4 manipulation was split, seemingly at random, between direct
(write_cr4) and using a helper (set/clear_in_cr4).  Unfortunately,
the set_in_cr4 and clear_in_cr4 helpers also poke at the boot code,
which only a small subset of users actually wanted.

This patch replaces all cr4 access in functions that don't leave cr4
exactly the way they found it with new helpers cr4_set_bits,
cr4_clear_bits, and cr4_set_bits_and_update_boot.

Signed-off-by: default avatarAndy Lutomirski <luto@amacapital.net>
Reviewed-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrea Arcangeli <aarcange@redhat.com>
Cc: Vince Weaver <vince@deater.net>
Cc: "hillf.zj" <hillf.zj@alibaba-inc.com>
Cc: Valdis Kletnieks <Valdis.Kletnieks@vt.edu>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Kees Cook <keescook@chromium.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: http://lkml.kernel.org/r/495a10bdc9e67016b8fd3945700d46cfd5c12c2f.1414190806.git.luto@amacapital.net


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 0967160a

arch/x86/include/asm/processor.h

+0 −33
Original line number Diff line number Diff line
@@ -579,39 +579,6 @@ static inline void load_sp0(struct tss_struct *tss, 
#define set_iopl_mask native_set_iopl_mask

#endif /* CONFIG_PARAVIRT */



/*

 * Save the cr4 feature set we're using (ie

 * Pentium 4MB enable and PPro Global page

 * enable), so that any CPU's that boot up

 * after us can get the correct flags.

 */

extern unsigned long mmu_cr4_features;

extern u32 *trampoline_cr4_features;



static inline void set_in_cr4(unsigned long mask)

{

	unsigned long cr4;



	mmu_cr4_features |= mask;

	if (trampoline_cr4_features)

		*trampoline_cr4_features = mmu_cr4_features;

	cr4 = read_cr4();

	cr4 |= mask;

	write_cr4(cr4);

}



static inline void clear_in_cr4(unsigned long mask)

{

	unsigned long cr4;



	mmu_cr4_features &= ~mask;

	if (trampoline_cr4_features)

		*trampoline_cr4_features = mmu_cr4_features;

	cr4 = read_cr4();

	cr4 &= ~mask;

	write_cr4(cr4);

}



typedef struct {

	unsigned long		seg;

} mm_segment_t;

arch/x86/include/asm/tlbflush.h

+37 −0
Original line number Diff line number Diff line
@@ -15,6 +15,43 @@ 
#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)

#endif



/* Set in this cpu's CR4. */

static inline void cr4_set_bits(unsigned long mask)

{

	unsigned long cr4;



	cr4 = read_cr4();

	cr4 |= mask;

	write_cr4(cr4);

}



/* Clear in this cpu's CR4. */

static inline void cr4_clear_bits(unsigned long mask)

{

	unsigned long cr4;



	cr4 = read_cr4();

	cr4 &= ~mask;

	write_cr4(cr4);

}



/*

 * Save some of cr4 feature set we're using (e.g.  Pentium 4MB

 * enable and PPro Global page enable), so that any CPU's that boot

 * up after us can get the correct flags.  This should only be used

 * during boot on the boot cpu.

 */

extern unsigned long mmu_cr4_features;

extern u32 *trampoline_cr4_features;



static inline void cr4_set_bits_and_update_boot(unsigned long mask)

{

	mmu_cr4_features |= mask;

	if (trampoline_cr4_features)

		*trampoline_cr4_features = mmu_cr4_features;

	cr4_set_bits(mask);

}



static inline void __native_flush_tlb(void)

{

	native_write_cr3(native_read_cr3());

arch/x86/include/asm/virtext.h

+2 −1
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 


#include <asm/vmx.h>

#include <asm/svm.h>

#include <asm/tlbflush.h>



/*

 * VMX functions:
@@ -40,7 +41,7 @@ static inline int cpu_has_vmx(void) 
static inline void cpu_vmxoff(void)

{

	asm volatile (ASM_VMX_VMXOFF : : : "cc");

	write_cr4(read_cr4() & ~X86_CR4_VMXE);

	cr4_clear_bits(X86_CR4_VMXE);

}



static inline int cpu_vmx_enabled(void)

arch/x86/kernel/cpu/common.c

+5 −5
Original line number Diff line number Diff line
@@ -278,7 +278,7 @@ __setup("nosmep", setup_disable_smep); 
static __always_inline void setup_smep(struct cpuinfo_x86 *c)

{

	if (cpu_has(c, X86_FEATURE_SMEP))

		set_in_cr4(X86_CR4_SMEP);

		cr4_set_bits(X86_CR4_SMEP);

}



static __init int setup_disable_smap(char *arg)
@@ -298,9 +298,9 @@ static __always_inline void setup_smap(struct cpuinfo_x86 *c) 


	if (cpu_has(c, X86_FEATURE_SMAP)) {

#ifdef CONFIG_X86_SMAP

		set_in_cr4(X86_CR4_SMAP);

		cr4_set_bits(X86_CR4_SMAP);

#else

		clear_in_cr4(X86_CR4_SMAP);

		cr4_clear_bits(X86_CR4_SMAP);

#endif

	}

}
@@ -1312,7 +1312,7 @@ void cpu_init(void) 


	pr_debug("Initializing CPU#%d\n", cpu);



	clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);

	cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);



	/*

	 * Initialize the per-CPU GDT with the boot GDT,
@@ -1393,7 +1393,7 @@ void cpu_init(void) 
	printk(KERN_INFO "Initializing CPU#%d\n", cpu);



	if (cpu_feature_enabled(X86_FEATURE_VME) || cpu_has_tsc || cpu_has_de)

		clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);

		cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);



	load_current_idt();

	switch_to_new_gdt(cpu);

arch/x86/kernel/cpu/mcheck/mce.c

+2 −1
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ 


#include <asm/processor.h>

#include <asm/traps.h>

#include <asm/tlbflush.h>

#include <asm/mce.h>

#include <asm/msr.h>
@@ -1449,7 +1450,7 @@ static void __mcheck_cpu_init_generic(void) 
	bitmap_fill(all_banks, MAX_NR_BANKS);

	machine_check_poll(MCP_UC | m_fl, &all_banks);



	set_in_cr4(X86_CR4_MCE);

	cr4_set_bits(X86_CR4_MCE);



	rdmsrl(MSR_IA32_MCG_CAP, cap);

	if (cap & MCG_CTL_P)