Merge branch 'x86/asm' into perf/x86, to avoid conflicts with upcoming patches

	xorl %ebx,%ebx

1:	ret

and the whole paranoid non-paranoid macro complexity is about whether

to suffer that RDMSR cost.

If we are at an interrupt or user-trap/gate-alike boundary then we can

use the faster check: the stack will be a reliable indicator of

whether SWAPGS was already done: if we see that we are a secondary

stack but before we executed SWAPGS, then the only safe way to check

for GS is the slower method: the RDMSR.

So we try only to mark those entry methods 'paranoid' that absolutely

need the more expensive check for the GS base - and we generate all

'normal' entry points with the regular (faster) entry macros.

Therefore, super-atomic entries (except NMI, which is handled separately)

must use idtentry with paranoid=1 to handle gsbase correctly.  This

triggers three main behavior changes:

 - Interrupt entry will use the slower gsbase check.

 - Interrupt entry from user mode will switch off the IST stack.

 - Interrupt exit to kernel mode will not attempt to reschedule.

We try to only use IST entries and the paranoid entry code for vectors

that absolutely need the more expensive check for the GS base - and we

generate all 'normal' entry points with the regular (faster) paranoid=0

variant.

interrupt-gate descriptor.  When an interrupt occurs and the hardware

loads such a descriptor, the hardware automatically sets the new stack

pointer based on the IST value, then invokes the interrupt handler.  If

software wants to allow nested IST interrupts then the handler must

adjust the IST values on entry to and exit from the interrupt handler.

(This is occasionally done, e.g. for debug exceptions.)

the interrupt came from user mode, then the interrupt handler prologue

will switch back to the per-thread stack.  If software wants to allow

nested IST interrupts then the handler must adjust the IST values on

entry to and exit from the interrupt handler.  (This is occasionally

done, e.g. for debug exceptions.)

Events with different IST codes (i.e. with different stacks) can be

nested.  For example, a debug interrupt can safely be interrupted by an

sysexit_from_sys_call:

	andl    $~TS_COMPAT,TI_status+THREAD_INFO(%rsp,RIP-ARGOFFSET)

	/* clear IF, that popfq doesn't enable interrupts early */

	andl  $~0x200,EFLAGS-R11(%rsp) 

	movl	RIP-R11(%rsp),%edx		/* User %eip */

	andl	$~0x200,EFLAGS-ARGOFFSET(%rsp)

	movl	RIP-ARGOFFSET(%rsp),%edx		/* User %eip */

	CFI_REGISTER rip,rdx

	RESTORE_ARGS 0,24,0,0,0,0

	xorq	%r8,%r8

#define SS		160

#define ARGOFFSET	R11

#define SWFRAME		ORIG_RAX

	.macro SAVE_ARGS addskip=0, save_rcx=1, save_r891011=1, rax_enosys=0

	subq  $9*8+\addskip, %rsp

void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);

int mce_notify_irq(void);

void mce_notify_process(void);

DECLARE_PER_CPU(struct mce, injectm);