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Commit 3423cab3 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branch 'for-next/perf' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux 

Support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU).

* 'for-next/perf' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux:
  perf: ARM DynamIQ Shared Unit PMU support
  dt-bindings: Document devicetree binding for ARM DSU PMU
  arm_pmu: Use of_cpu_node_to_id helper
  arm64: Use of_cpu_node_to_id helper for CPU topology parsing
  irqchip: gic-v3: Use of_cpu_node_to_id helper
  coresight: of: Use of_cpu_node_to_id helper
  of: Add helper for mapping device node to logical CPU number
  perf: Export perf_event_update_userpage
parents 0d907188 7520fa99

Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt

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* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)



ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores

with a shared L3 memory system, control logic and external interfaces to

form a multicore cluster. The PMU enables to gather various statistics on

the operations of the DSU. The PMU provides independent 32bit counters that

can count any of the supported events, along with a 64bit cycle counter.

The PMU is accessed via CPU system registers and has no MMIO component.



** DSU PMU required properties:



- compatible	: should be one of :



		"arm,dsu-pmu"



- interrupts	: Exactly 1 SPI must be listed.



- cpus		: List of phandles for the CPUs connected to this DSU instance.





** Example:



dsu-pmu-0 {

	compatible = "arm,dsu-pmu";

	interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;

	cpus = <&cpu_0>, <&cpu_1>;

};

Documentation/perf/arm_dsu_pmu.txt

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ARM DynamIQ Shared Unit (DSU) PMU

==================================



ARM DynamIQ Shared Unit integrates one or more cores with an L3 memory system,

control logic and external interfaces to form a multicore cluster. The PMU

allows counting the various events related to the L3 cache, Snoop Control Unit

etc, using 32bit independent counters. It also provides a 64bit cycle counter.



The PMU can only be accessed via CPU system registers and are common to the

cores connected to the same DSU. Like most of the other uncore PMUs, DSU

PMU doesn't support process specific events and cannot be used in sampling mode.



The DSU provides a bitmap for a subset of implemented events via hardware

registers. There is no way for the driver to determine if the other events

are available or not. Hence the driver exposes only those events advertised

by the DSU, in "events" directory under :



  /sys/bus/event_sources/devices/arm_dsu_<N>/



The user should refer to the TRM of the product to figure out the supported events

and use the raw event code for the unlisted events.



The driver also exposes the CPUs connected to the DSU instance in "associated_cpus".





e.g usage :



	perf stat -a -e arm_dsu_0/cycles/

arch/arm64/include/asm/arm_dsu_pmu.h

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/*

 * ARM DynamIQ Shared Unit (DSU) PMU Low level register access routines.

 *

 * Copyright (C) ARM Limited, 2017.

 *

 * Author: Suzuki K Poulose <suzuki.poulose@arm.com>

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License

 * version 2, as published by the Free Software Foundation.

 */



#include <linux/bitops.h>

#include <linux/build_bug.h>

#include <linux/compiler.h>

#include <linux/types.h>

#include <asm/barrier.h>

#include <asm/sysreg.h>





#define CLUSTERPMCR_EL1			sys_reg(3, 0, 15, 5, 0)

#define CLUSTERPMCNTENSET_EL1		sys_reg(3, 0, 15, 5, 1)

#define CLUSTERPMCNTENCLR_EL1		sys_reg(3, 0, 15, 5, 2)

#define CLUSTERPMOVSSET_EL1		sys_reg(3, 0, 15, 5, 3)

#define CLUSTERPMOVSCLR_EL1		sys_reg(3, 0, 15, 5, 4)

#define CLUSTERPMSELR_EL1		sys_reg(3, 0, 15, 5, 5)

#define CLUSTERPMINTENSET_EL1		sys_reg(3, 0, 15, 5, 6)

#define CLUSTERPMINTENCLR_EL1		sys_reg(3, 0, 15, 5, 7)

#define CLUSTERPMCCNTR_EL1		sys_reg(3, 0, 15, 6, 0)

#define CLUSTERPMXEVTYPER_EL1		sys_reg(3, 0, 15, 6, 1)

#define CLUSTERPMXEVCNTR_EL1		sys_reg(3, 0, 15, 6, 2)

#define CLUSTERPMMDCR_EL1		sys_reg(3, 0, 15, 6, 3)

#define CLUSTERPMCEID0_EL1		sys_reg(3, 0, 15, 6, 4)

#define CLUSTERPMCEID1_EL1		sys_reg(3, 0, 15, 6, 5)



static inline u32 __dsu_pmu_read_pmcr(void)

{

	return read_sysreg_s(CLUSTERPMCR_EL1);

}



static inline void __dsu_pmu_write_pmcr(u32 val)

{

	write_sysreg_s(val, CLUSTERPMCR_EL1);

	isb();

}



static inline u32 __dsu_pmu_get_reset_overflow(void)

{

	u32 val = read_sysreg_s(CLUSTERPMOVSCLR_EL1);

	/* Clear the bit */

	write_sysreg_s(val, CLUSTERPMOVSCLR_EL1);

	isb();

	return val;

}



static inline void __dsu_pmu_select_counter(int counter)

{

	write_sysreg_s(counter, CLUSTERPMSELR_EL1);

	isb();

}



static inline u64 __dsu_pmu_read_counter(int counter)

{

	__dsu_pmu_select_counter(counter);

	return read_sysreg_s(CLUSTERPMXEVCNTR_EL1);

}



static inline void __dsu_pmu_write_counter(int counter, u64 val)

{

	__dsu_pmu_select_counter(counter);

	write_sysreg_s(val, CLUSTERPMXEVCNTR_EL1);

	isb();

}



static inline void __dsu_pmu_set_event(int counter, u32 event)

{

	__dsu_pmu_select_counter(counter);

	write_sysreg_s(event, CLUSTERPMXEVTYPER_EL1);

	isb();

}



static inline u64 __dsu_pmu_read_pmccntr(void)

{

	return read_sysreg_s(CLUSTERPMCCNTR_EL1);

}



static inline void __dsu_pmu_write_pmccntr(u64 val)

{

	write_sysreg_s(val, CLUSTERPMCCNTR_EL1);

	isb();

}



static inline void __dsu_pmu_disable_counter(int counter)

{

	write_sysreg_s(BIT(counter), CLUSTERPMCNTENCLR_EL1);

	isb();

}



static inline void __dsu_pmu_enable_counter(int counter)

{

	write_sysreg_s(BIT(counter), CLUSTERPMCNTENSET_EL1);

	isb();

}



static inline void __dsu_pmu_counter_interrupt_enable(int counter)

{

	write_sysreg_s(BIT(counter), CLUSTERPMINTENSET_EL1);

	isb();

}



static inline void __dsu_pmu_counter_interrupt_disable(int counter)

{

	write_sysreg_s(BIT(counter), CLUSTERPMINTENCLR_EL1);

	isb();

}





static inline u32 __dsu_pmu_read_pmceid(int n)

{

	switch (n) {

	case 0:

		return read_sysreg_s(CLUSTERPMCEID0_EL1);

	case 1:

		return read_sysreg_s(CLUSTERPMCEID1_EL1);

	default:

		BUILD_BUG();

		return 0;

	}

}

arch/arm64/kernel/topology.c

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@@ -37,18 +37,14 @@ static int __init get_cpu_for_node(struct device_node *node) 
	if (!cpu_node)

		return -1;



	for_each_possible_cpu(cpu) {

		if (of_get_cpu_node(cpu, NULL) == cpu_node) {

	cpu = of_cpu_node_to_id(cpu_node);

	if (cpu >= 0)

		topology_parse_cpu_capacity(cpu_node, cpu);

			of_node_put(cpu_node);

			return cpu;

		}

	}



	else

		pr_crit("Unable to find CPU node for %pOF\n", cpu_node);



	of_node_put(cpu_node);

	return -1;

	return cpu;

}



static int __init parse_core(struct device_node *core, int cluster_id,

drivers/hwtracing/coresight/of_coresight.c

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@@ -104,26 +104,17 @@ static int of_coresight_alloc_memory(struct device *dev, 
int of_coresight_get_cpu(const struct device_node *node)

{

	int cpu;

	bool found;

	struct device_node *dn, *np;

	struct device_node *dn;



	dn = of_parse_phandle(node, "cpu", 0);



	/* Affinity defaults to CPU0 */

	if (!dn)

		return 0;



	for_each_possible_cpu(cpu) {

		np = of_cpu_device_node_get(cpu);

		found = (dn == np);

		of_node_put(np);

		if (found)

			break;

	}

	cpu = of_cpu_node_to_id(dn);

	of_node_put(dn);



	/* Affinity to CPU0 if no cpu nodes are found */

	return found ? cpu : 0;

	return (cpu < 0) ? 0 : cpu;

}

EXPORT_SYMBOL_GPL(of_coresight_get_cpu);