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Commit 0d907188 authored by Jayachandran C's avatar Jayachandran C Committed by Catalin Marinas
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arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs 



Add the older Broadcom ID as well as the new Cavium ID for ThunderX2
CPUs.

Signed-off-by: default avatarJayachandran C <jnair@caviumnetworks.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent ec82b567

arch/arm64/include/asm/cputype.h

+3 −0
Original line number Diff line number Diff line
@@ -89,6 +89,7 @@ 
#define CAVIUM_CPU_PART_THUNDERX	0x0A1

#define CAVIUM_CPU_PART_THUNDERX_81XX	0x0A2

#define CAVIUM_CPU_PART_THUNDERX_83XX	0x0A3

#define CAVIUM_CPU_PART_THUNDERX2	0x0AF



#define BRCM_CPU_PART_VULCAN		0x516
@@ -102,6 +103,8 @@ 
#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)

#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)

#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)



#ifndef __ASSEMBLY__