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Commit 305b5475 authored by Paweł Jarosz's avatar Paweł Jarosz Committed by Heiko Stuebner
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ARM: dts: rockchip: initialize rk3066 PLL clock rate 



Initialize PLL, cpu bus and peripherial bus rate while kernel init.
No other module does than.

This gives us performance boost observable for example in mmc transfers.

Signed-off-by: default avatarPaweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 30522550

arch/arm/boot/dts/rk3066a.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -151,6 +151,14 @@ 


		#clock-cells = <1>;

		#reset-cells = <1>;

		assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,

				  <&cru ACLK_CPU>, <&cru HCLK_CPU>,

				  <&cru PCLK_CPU>, <&cru ACLK_PERI>,

				  <&cru HCLK_PERI>, <&cru PCLK_PERI>;

		assigned-clock-rates = <400000000>, <594000000>,

				       <300000000>, <150000000>,

				       <75000000>, <300000000>,

				       <150000000>, <75000000>;

	};



	timer@2000e000 {