Loading include/dt-bindings/clock/rk3188-cru-common.h +7 −1 Original line number Diff line number Diff line Loading @@ -72,6 +72,8 @@ #define ACLK_IPP 200 #define ACLK_RGA 201 #define ACLK_CIF0 202 #define ACLK_CPU 203 #define ACLK_PERI 204 /* pclk gates */ #define PCLK_GRF 320 Loading Loading @@ -104,6 +106,8 @@ #define PCLK_EFUSE 347 #define PCLK_TZPC 348 #define PCLK_TSADC 349 #define PCLK_CPU 350 #define PCLK_PERI 351 /* hclk gates */ #define HCLK_SDMMC 448 Loading @@ -126,8 +130,10 @@ #define HCLK_IPP 465 #define HCLK_RGA 466 #define HCLK_NANDC0 467 #define HCLK_CPU 468 #define HCLK_PERI 469 #define CLK_NR_CLKS (HCLK_NANDC0 + 1) #define CLK_NR_CLKS (HCLK_PERI + 1) /* soft-reset indices */ #define SRST_MCORE 2 Loading Loading
include/dt-bindings/clock/rk3188-cru-common.h +7 −1 Original line number Diff line number Diff line Loading @@ -72,6 +72,8 @@ #define ACLK_IPP 200 #define ACLK_RGA 201 #define ACLK_CIF0 202 #define ACLK_CPU 203 #define ACLK_PERI 204 /* pclk gates */ #define PCLK_GRF 320 Loading Loading @@ -104,6 +106,8 @@ #define PCLK_EFUSE 347 #define PCLK_TZPC 348 #define PCLK_TSADC 349 #define PCLK_CPU 350 #define PCLK_PERI 351 /* hclk gates */ #define HCLK_SDMMC 448 Loading @@ -126,8 +130,10 @@ #define HCLK_IPP 465 #define HCLK_RGA 466 #define HCLK_NANDC0 467 #define HCLK_CPU 468 #define HCLK_PERI 469 #define CLK_NR_CLKS (HCLK_NANDC0 + 1) #define CLK_NR_CLKS (HCLK_PERI + 1) /* soft-reset indices */ #define SRST_MCORE 2 Loading