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Commit 2bbf6078 authored by Mark Brown's avatar Mark Brown
Browse files

Merge branch 'asoc-omap' into for-3.7

parents 02e79476 b8101048

Documentation/devicetree/bindings/sound/omap-mcbsp.txt

0 → 100644
+37 −0
Original line number Original line Diff line number Diff line 
* Texas Instruments OMAP2+ McBSP module



Required properties:

- compatible: "ti,omap2420-mcbsp" for McBSP on OMAP2420

	      "ti,omap2430-mcbsp" for McBSP on OMAP2430

	      "ti,omap3-mcbsp" for McBSP on OMAP3

	      "ti,omap4-mcbsp" for McBSP on OMAP4 and newer SoC

- reg: Register location and size, for OMAP4+ as an array:

       <MPU access base address, size>,

       <L3 interconnect address, size>;

- reg-names: Array of strings associated with the address space

- interrupts: Interrupt numbers for the McBSP port, as an array in case the

	      McBSP IP have more interrupt lines:

	<OCP compliant irq>,

	<TX irq>,

	<RX irq>;

- interrupt-names: Array of strings associated with the interrupt numbers

- interrupt-parent: The parent interrupt controller

- ti,buffer-size: Size of the FIFO on the port (OMAP2430 and newer SoC)

- ti,hwmods: Name of the hwmod associated to the McBSP port



Example:



mcbsp2: mcbsp@49022000 {

	compatible = "ti,omap3-mcbsp";

	reg = <0x49022000 0xff>,

	      <0x49028000 0xff>;

	reg-names = "mpu", "sidetone";

	interrupts = <0 17 0x4>, /* OCP compliant interrupt */

		     <0 62 0x4>, /* TX interrupt */

		     <0 63 0x4>, /* RX interrupt */

		     <0 4 0x4>;  /* Sidetone */

	interrupt-names = "common", "tx", "rx", "sidetone";

	interrupt-parent = <&intc>;

	ti,buffer-size = <1280>;

	ti,hwmods = "mcbsp2";

};

arch/arm/mach-omap2/board-am3517evm.c

+13 −0
Original line number Original line Diff line number Diff line
@@ -264,6 +264,16 @@ static __init void am3517_evm_musb_init(void) 
	usb_musb_init(&musb_board_data);

	usb_musb_init(&musb_board_data);

}

}





static __init void am3517_evm_mcbsp1_init(void)

{

	u32 devconf0;



	/* McBSP1 CLKR/FSR signal to be connected to CLKX/FSX pin */

	devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);

	devconf0 |=  OMAP2_MCBSP1_CLKR_MASK | OMAP2_MCBSP1_FSR_MASK;

	omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);

}



static const struct usbhs_omap_board_data usbhs_bdata __initconst = {

static const struct usbhs_omap_board_data usbhs_bdata __initconst = {

	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,

	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,

#if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \

#if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
@@ -373,6 +383,9 @@ static void __init am3517_evm_init(void) 
	/* MUSB */

	/* MUSB */

	am3517_evm_musb_init();

	am3517_evm_musb_init();





	/* McBSP1 */

	am3517_evm_mcbsp1_init();



	/* MMC init function */

	/* MMC init function */

	omap_hsmmc_init(mmc);

	omap_hsmmc_init(mmc);

}

}

arch/arm/mach-omap2/mcbsp.c

+7 −119
Original line number Original line Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <linux/clk.h>

#include <linux/clk.h>

#include <linux/err.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/io.h>

#include <linux/of.h>

#include <linux/platform_device.h>

#include <linux/platform_device.h>

#include <linux/slab.h>

#include <linux/slab.h>
@@ -25,8 +26,6 @@ 
#include <plat/omap_device.h>

#include <plat/omap_device.h>

#include <linux/pm_runtime.h>

#include <linux/pm_runtime.h>





#include "control.h"



/*

/*

 * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.

 * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.

 * Sidetone needs non-gated ICLK and sidetone autoidle is broken.

 * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
@@ -34,112 +33,6 @@ 
#include "cm2xxx_3xxx.h"

#include "cm2xxx_3xxx.h"

#include "cm-regbits-34xx.h"

#include "cm-regbits-34xx.h"





/* McBSP1 internal signal muxing function for OMAP2/3 */

static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,

				   const char *src)

{

	u32 v;



	v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);



	if (!strcmp(signal, "clkr")) {

		if (!strcmp(src, "clkr"))

			v &= ~OMAP2_MCBSP1_CLKR_MASK;

		else if (!strcmp(src, "clkx"))

			v |= OMAP2_MCBSP1_CLKR_MASK;

		else

			return -EINVAL;

	} else if (!strcmp(signal, "fsr")) {

		if (!strcmp(src, "fsr"))

			v &= ~OMAP2_MCBSP1_FSR_MASK;

		else if (!strcmp(src, "fsx"))

			v |= OMAP2_MCBSP1_FSR_MASK;

		else

			return -EINVAL;

	} else {

		return -EINVAL;

	}



	omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);



	return 0;

}



/* McBSP4 internal signal muxing function for OMAP4 */

#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX	(1 << 31)

#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX	(1 << 30)

static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,

				   const char *src)

{

	u32 v;



	/*

	 * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR

	 * mux) is used */

	v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);



	if (!strcmp(signal, "clkr")) {

		if (!strcmp(src, "clkr"))

			v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;

		else if (!strcmp(src, "clkx"))

			v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;

		else

			return -EINVAL;

	} else if (!strcmp(signal, "fsr")) {

		if (!strcmp(src, "fsr"))

			v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;

		else if (!strcmp(src, "fsx"))

			v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;

		else

			return -EINVAL;

	} else {

		return -EINVAL;

	}



	omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);



	return 0;

}



/* McBSP CLKS source switching function */

static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk,

				   const char *src)

{

	struct clk *fck_src;

	char *fck_src_name;

	int r;



	if (!strcmp(src, "clks_ext"))

		fck_src_name = "pad_fck";

	else if (!strcmp(src, "clks_fclk"))

		fck_src_name = "prcm_fck";

	else

		return -EINVAL;



	fck_src = clk_get(dev, fck_src_name);

	if (IS_ERR_OR_NULL(fck_src)) {

		pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",

		       fck_src_name);

		return -EINVAL;

	}



	pm_runtime_put_sync(dev);



	r = clk_set_parent(clk, fck_src);

	if (IS_ERR_VALUE(r)) {

		pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",

		       "clks", fck_src_name);

		clk_put(fck_src);

		return -EINVAL;

	}



	pm_runtime_get_sync(dev);



	clk_put(fck_src);



	return 0;

}



static int omap3_enable_st_clock(unsigned int id, bool enable)

static int omap3_enable_st_clock(unsigned int id, bool enable)

{

{

	unsigned int w;

	unsigned int w;
@@ -181,17 +74,11 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) 
		pdata->reg_size = 4;

		pdata->reg_size = 4;

		pdata->has_ccr = true;

		pdata->has_ccr = true;

	}

	}

	pdata->set_clk_src = omap2_mcbsp_set_clk_src;



	/* On OMAP2/3 the McBSP1 port has 6 pin configuration */

	if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)

		pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;



	/* On OMAP4 the McBSP4 port has 6 pin configuration */

	if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)

		pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;





	if (oh->class->rev == MCBSP_CONFIG_TYPE3) {

	if (oh->class->rev == MCBSP_CONFIG_TYPE2) {

		/* The FIFO has 128 locations */

		pdata->buffer_size = 0x80;

	} else if (oh->class->rev == MCBSP_CONFIG_TYPE3) {

		if (id == 2)

		if (id == 2)

			/* The FIFO has 1024 + 256 locations */

			/* The FIFO has 1024 + 256 locations */

			pdata->buffer_size = 0x500;

			pdata->buffer_size = 0x500;
@@ -227,6 +114,7 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) 




static int __init omap2_mcbsp_init(void)

static int __init omap2_mcbsp_init(void)

{

{

	if (!of_have_populated_dt())

		omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);

		omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);





	return 0;

	return 0;

arch/arm/plat-omap/include/plat/mcbsp.h

+0 −2
Original line number Original line Diff line number Diff line
@@ -47,8 +47,6 @@ struct omap_mcbsp_platform_data { 
	bool has_wakeup; /* Wakeup capability */

	bool has_wakeup; /* Wakeup capability */

	bool has_ccr; /* Transceiver has configuration control registers */

	bool has_ccr; /* Transceiver has configuration control registers */

	int (*enable_st_clock)(unsigned int, bool);

	int (*enable_st_clock)(unsigned int, bool);

	int (*set_clk_src)(struct device *dev, struct clk *clk, const char *src);

	int (*mux_signal)(struct device *dev, const char *signal, const char *src);

};

};





/**

/**

sound/soc/omap/am3517evm.c

+2 −18
Original line number Original line Diff line number Diff line
@@ -47,28 +47,12 @@ static int am3517evm_hw_params(struct snd_pcm_substream *substream, 
	/* Set the codec system clock for DAC and ADC */

	/* Set the codec system clock for DAC and ADC */

	ret = snd_soc_dai_set_sysclk(codec_dai, 0,

	ret = snd_soc_dai_set_sysclk(codec_dai, 0,

			CODEC_CLOCK, SND_SOC_CLOCK_IN);

			CODEC_CLOCK, SND_SOC_CLOCK_IN);

	if (ret < 0) {

	if (ret < 0)

		printk(KERN_ERR "can't set codec system clock\n");

		printk(KERN_ERR "can't set codec system clock\n");

		return ret;

	}



	ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_CLKR_SRC_CLKX, 0,

				SND_SOC_CLOCK_IN);

	if (ret < 0) {

		printk(KERN_ERR "can't set CPU system clock OMAP_MCBSP_CLKR_SRC_CLKX\n");

		return ret;

	}





	snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_FSR_SRC_FSX, 0,

				SND_SOC_CLOCK_IN);

	if (ret < 0) {

		printk(KERN_ERR "can't set CPU system clock OMAP_MCBSP_FSR_SRC_FSX\n");

	return ret;

	return ret;

}

}





	return 0;

}



static struct snd_soc_ops am3517evm_ops = {

static struct snd_soc_ops am3517evm_ops = {

	.hw_params = am3517evm_hw_params,

	.hw_params = am3517evm_hw_params,

};

};