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Commit 28cf3567 authored by Hao Liu's avatar Hao Liu Committed by Daniel Lezcano
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clocksource: sirf: Disable counter before re-setting it 



According to HW spec, we have to disable the counter before setting
it, if we don't this, in pressure test, sometimes the timer might
not generate interrupt any more.

And this patch also fixes a typo for register set by changing 0x7
to 0x3. 0x7 is loop mode in HW, but here we are using oneshot 0x3.

Signed-off-by: default avatarHao Liu <Hao.Liu@csr.com>
Signed-off-by: default avatarBarry Song <Baohua.Song@csr.com>
Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
parent 4e2bec0c

drivers/clocksource/timer-marco.c

+4 −1
Original line number Original line Diff line number Diff line
@@ -63,7 +63,7 @@ static inline void sirfsoc_timer_count_disable(int idx) 
/* enable count and interrupt */

/* enable count and interrupt */

static inline void sirfsoc_timer_count_enable(int idx)

static inline void sirfsoc_timer_count_enable(int idx)

{

{

	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7,

	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3,

		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);

		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);

}

}
@@ -103,6 +103,9 @@ static int sirfsoc_timer_set_next_event(unsigned long delta, 
{

{

	int cpu = smp_processor_id();

	int cpu = smp_processor_id();





	/* disable timer first, then modify the related registers */

	sirfsoc_timer_count_disable(cpu);



	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +

	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +

		4 * cpu);

		4 * cpu);

	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +

	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +