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Commit 267ba964 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Will Deacon:
 "A couple of late fixes here, but one that we've been sitting on for a
  few weeks while the details were worked out.  Specifically, we now
  enforce USER_DS on taking exceptions whilst in the kernel, which
  avoids leaking kernel data to userspace through things like perf.  The
  other patch is an update to a workaround for a hardware erratum on
  some Cavium SoCs.

  Summary:

   - Enforce USER_DS on exception entry from EL1

   - Apply workaround for Cavium errata #27456 on Thunderx-81xx parts"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: Enable workaround for Cavium erratum 27456 on thunderx-81xx
  arm64: kernel: Save and restore UAO and addr_limit on exception entry
parents a017f583 47c459be

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -80,12 +80,14 @@ 
#define APM_CPU_PART_POTENZA		0x000



#define CAVIUM_CPU_PART_THUNDERX	0x0A1

#define CAVIUM_CPU_PART_THUNDERX_81XX	0x0A2



#define BRCM_CPU_PART_VULCAN		0x516



#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)

#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)



#ifndef __ASSEMBLY__

arch/arm64/include/asm/ptrace.h

+2 −0
Original line number Diff line number Diff line
@@ -117,6 +117,8 @@ struct pt_regs { 
	};

	u64 orig_x0;

	u64 syscallno;

	u64 orig_addr_limit;

	u64 unused;	// maintain 16 byte alignment

};



#define arch_has_single_step()	(1)

arch/arm64/kernel/asm-offsets.c

+1 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ int main(void) 
  DEFINE(S_PC,			offsetof(struct pt_regs, pc));

  DEFINE(S_ORIG_X0,		offsetof(struct pt_regs, orig_x0));

  DEFINE(S_SYSCALLNO,		offsetof(struct pt_regs, syscallno));

  DEFINE(S_ORIG_ADDR_LIMIT,	offsetof(struct pt_regs, orig_addr_limit));

  DEFINE(S_FRAME_SIZE,		sizeof(struct pt_regs));

  BLANK();

  DEFINE(MM_CONTEXT_ID,		offsetof(struct mm_struct, context.id.counter));

arch/arm64/kernel/cpu_errata.c

+6 −0
Original line number Diff line number Diff line
@@ -98,6 +98,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		MIDR_RANGE(MIDR_THUNDERX, 0x00,

			   (1 << MIDR_VARIANT_SHIFT) | 1),

	},

	{

	/* Cavium ThunderX, T81 pass 1.0 */

		.desc = "Cavium erratum 27456",

		.capability = ARM64_WORKAROUND_CAVIUM_27456,

		MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),

	},

#endif

	{

	}

arch/arm64/kernel/entry.S

+17 −2
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
#include <asm/errno.h>

#include <asm/esr.h>

#include <asm/irq.h>

#include <asm/memory.h>

#include <asm/thread_info.h>

#include <asm/unistd.h>
@@ -97,7 +98,14 @@ 
	mov	x29, xzr			// fp pointed to user-space

	.else

	add	x21, sp, #S_FRAME_SIZE

	.endif

	get_thread_info tsk

	/* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */

	ldr	x20, [tsk, #TI_ADDR_LIMIT]

	str	x20, [sp, #S_ORIG_ADDR_LIMIT]

	mov	x20, #TASK_SIZE_64

	str	x20, [tsk, #TI_ADDR_LIMIT]

	ALTERNATIVE(nop, SET_PSTATE_UAO(0), ARM64_HAS_UAO, CONFIG_ARM64_UAO)

	.endif /* \el == 0 */

	mrs	x22, elr_el1

	mrs	x23, spsr_el1

	stp	lr, x21, [sp, #S_LR]
@@ -128,6 +136,14 @@ 
	.endm



	.macro	kernel_exit, el

	.if	\el != 0

	/* Restore the task's original addr_limit. */

	ldr	x20, [sp, #S_ORIG_ADDR_LIMIT]

	str	x20, [tsk, #TI_ADDR_LIMIT]



	/* No need to restore UAO, it will be restored from SPSR_EL1 */

	.endif



	ldp	x21, x22, [sp, #S_PC]		// load ELR, SPSR

	.if	\el == 0

	ct_user_enter
@@ -406,7 +422,6 @@ el1_irq: 
	bl	trace_hardirqs_off

#endif



	get_thread_info tsk

	irq_handler



#ifdef CONFIG_PREEMPT