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Commit 47c459be authored by Ganapatrao Kulkarni's avatar Ganapatrao Kulkarni Committed by Will Deacon
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arm64: Enable workaround for Cavium erratum 27456 on thunderx-81xx 



Cavium erratum 27456 commit 104a0c02
("arm64: Add workaround for Cavium erratum 27456")
is applicable for thunderx-81xx pass1.0 SoC as well.
Adding code to enable to 81xx.

Signed-off-by: default avatarGanapatrao Kulkarni <gkulkarni@cavium.com>
Reviewed-by: default avatarAndrew Pinski <apinski@cavium.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent e19a6ee2

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -80,12 +80,14 @@ 
#define APM_CPU_PART_POTENZA		0x000



#define CAVIUM_CPU_PART_THUNDERX	0x0A1

#define CAVIUM_CPU_PART_THUNDERX_81XX	0x0A2



#define BRCM_CPU_PART_VULCAN		0x516



#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)

#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)



#ifndef __ASSEMBLY__

arch/arm64/kernel/cpu_errata.c

+6 −0
Original line number Diff line number Diff line
@@ -98,6 +98,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		MIDR_RANGE(MIDR_THUNDERX, 0x00,

			   (1 << MIDR_VARIANT_SHIFT) | 1),

	},

	{

	/* Cavium ThunderX, T81 pass 1.0 */

		.desc = "Cavium erratum 27456",

		.capability = ARM64_WORKAROUND_CAVIUM_27456,

		MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),

	},

#endif

	{

	}