Loading arch/arm64/boot/dts/qcom/kona.dtsi +4 −4 Original line number Diff line number Diff line Loading @@ -189,7 +189,7 @@ next-level-cache = <&L2_4>; qcom,freq-domain = <&cpufreq_hw 1 4>; capacity-dmips-mhz = <1894>; dynamic-power-coefficient = <374>; dynamic-power-coefficient = <514>; L2_4: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x40000>; Loading Loading @@ -231,7 +231,7 @@ next-level-cache = <&L2_5>; qcom,freq-domain = <&cpufreq_hw 1 4>; capacity-dmips-mhz = <1894>; dynamic-power-coefficient = <374>; dynamic-power-coefficient = <514>; L2_5: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x40000>; Loading Loading @@ -273,7 +273,7 @@ next-level-cache = <&L2_6>; qcom,freq-domain = <&cpufreq_hw 1 4>; capacity-dmips-mhz = <1894>; dynamic-power-coefficient = <374>; dynamic-power-coefficient = <514>; L2_6: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x40000>; Loading Loading @@ -315,7 +315,7 @@ next-level-cache = <&L2_7>; qcom,freq-domain = <&cpufreq_hw 2 4>; capacity-dmips-mhz = <1894>; dynamic-power-coefficient = <431>; dynamic-power-coefficient = <598>; L2_7: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x80000>; Loading Loading
arch/arm64/boot/dts/qcom/kona.dtsi +4 −4 Original line number Diff line number Diff line Loading @@ -189,7 +189,7 @@ next-level-cache = <&L2_4>; qcom,freq-domain = <&cpufreq_hw 1 4>; capacity-dmips-mhz = <1894>; dynamic-power-coefficient = <374>; dynamic-power-coefficient = <514>; L2_4: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x40000>; Loading Loading @@ -231,7 +231,7 @@ next-level-cache = <&L2_5>; qcom,freq-domain = <&cpufreq_hw 1 4>; capacity-dmips-mhz = <1894>; dynamic-power-coefficient = <374>; dynamic-power-coefficient = <514>; L2_5: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x40000>; Loading Loading @@ -273,7 +273,7 @@ next-level-cache = <&L2_6>; qcom,freq-domain = <&cpufreq_hw 1 4>; capacity-dmips-mhz = <1894>; dynamic-power-coefficient = <374>; dynamic-power-coefficient = <514>; L2_6: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x40000>; Loading Loading @@ -315,7 +315,7 @@ next-level-cache = <&L2_7>; qcom,freq-domain = <&cpufreq_hw 2 4>; capacity-dmips-mhz = <1894>; dynamic-power-coefficient = <431>; dynamic-power-coefficient = <598>; L2_7: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x80000>; Loading