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Commit db98c3e6 authored by Satya Durga Srinivasu Prabhala's avatar Satya Durga Srinivasu Prabhala
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ARM: dts: msm: update dynamic-power-coefficient property for Kona 



Update "dynamic-power-coefficient" for Gold and Gold+ cores per
latest data.

Change-Id: I432d2496ee74e7ec6f26b118554cfc1ee4ba547c
Signed-off-by: default avatarSatya Durga Srinivasu Prabhala <satyap@codeaurora.org>
parent 3b3e314b

arch/arm64/boot/dts/qcom/kona.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -189,7 +189,7 @@ 
			next-level-cache = <&L2_4>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			capacity-dmips-mhz = <1894>;

			dynamic-power-coefficient = <374>;

			dynamic-power-coefficient = <514>;

			L2_4: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x40000>;
@@ -231,7 +231,7 @@ 
			next-level-cache = <&L2_5>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			capacity-dmips-mhz = <1894>;

			dynamic-power-coefficient = <374>;

			dynamic-power-coefficient = <514>;

			L2_5: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x40000>;
@@ -273,7 +273,7 @@ 
			next-level-cache = <&L2_6>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			capacity-dmips-mhz = <1894>;

			dynamic-power-coefficient = <374>;

			dynamic-power-coefficient = <514>;

			L2_6: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x40000>;
@@ -315,7 +315,7 @@ 
			next-level-cache = <&L2_7>;

			qcom,freq-domain = <&cpufreq_hw 2 4>;

			capacity-dmips-mhz = <1894>;

			dynamic-power-coefficient = <431>;

			dynamic-power-coefficient = <598>;

			L2_7: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x80000>;