Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 25642705 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by Michael Ellerman
Browse files

powerpc/xive: Fix offset for store EOI MMIOs 



Architecturally we should apply a 0x400 offset for these. Not doing
it will break future HW implementations.

The offset of 0 is supposed to remain for "triggers" though not all
sources support both trigger and store EOI, and in P9 specifically,
some sources will treat 0 as a store EOI. But future chips will not.
So this makes us use the properly architected offset which should work
always.

Fixes: 243e2511 ("powerpc/xive: Native exploitation of the XIVE interrupt controller")
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 377aa6b0

arch/powerpc/include/asm/xive.h

+7 −5
Original line number Diff line number Diff line
@@ -94,11 +94,13 @@ struct xive_q { 
 * store at 0 and some ESBs support doing a trigger via a

 * separate trigger page.

 */

#define XIVE_ESB_GET		0x800

#define XIVE_ESB_SET_PQ_00	0xc00

#define XIVE_ESB_SET_PQ_01	0xd00

#define XIVE_ESB_SET_PQ_10	0xe00

#define XIVE_ESB_SET_PQ_11	0xf00

#define XIVE_ESB_STORE_EOI	0x400 /* Store */

#define XIVE_ESB_LOAD_EOI	0x000 /* Load */

#define XIVE_ESB_GET		0x800 /* Load */

#define XIVE_ESB_SET_PQ_00	0xc00 /* Load */

#define XIVE_ESB_SET_PQ_01	0xd00 /* Load */

#define XIVE_ESB_SET_PQ_10	0xe00 /* Load */

#define XIVE_ESB_SET_PQ_11	0xf00 /* Load */



#define XIVE_ESB_VAL_P		0x2

#define XIVE_ESB_VAL_Q		0x1

arch/powerpc/kvm/book3s_xive_template.c

+2 −2
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ static void GLUE(X_PFX,source_eoi)(u32 hw_irq, struct xive_irq_data *xd) 
{

	/* If the XIVE supports the new "store EOI facility, use it */

	if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)

		__x_writeq(0, __x_eoi_page(xd));

		__x_writeq(0, __x_eoi_page(xd) + XIVE_ESB_STORE_EOI);

	else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW) {

		opal_int_eoi(hw_irq);

	} else {
@@ -89,7 +89,7 @@ static void GLUE(X_PFX,source_eoi)(u32 hw_irq, struct xive_irq_data *xd) 
		 * properly.

		 */

		if (xd->flags & XIVE_IRQ_FLAG_LSI)

			__x_readq(__x_eoi_page(xd));

			__x_readq(__x_eoi_page(xd) + XIVE_ESB_LOAD_EOI);

		else {

			eoi_val = GLUE(X_PFX,esb_load)(xd, XIVE_ESB_SET_PQ_00);

arch/powerpc/sysdev/xive/common.c

+1 −1
Original line number Diff line number Diff line
@@ -297,7 +297,7 @@ void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd) 
{

	/* If the XIVE supports the new "store EOI facility, use it */

	if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)

		out_be64(xd->eoi_mmio, 0);

		out_be64(xd->eoi_mmio + XIVE_ESB_STORE_EOI, 0);

	else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW) {

		/*

		 * The FW told us to call it. This happens for some