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Commit 2517caf1 authored by John Crispin's avatar John Crispin Committed by Ralf Baechle
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MIPS: ralink: Add missing I2C and I2S clocks. 



This patch adds two additional clocks required by the audio interface of
the SoCs.

Signed-off-by: default avatarJohn Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14897/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 4f79ddec

arch/mips/ralink/mt7620.c

+5 −0
Original line number Diff line number Diff line
@@ -509,6 +509,7 @@ void __init ralink_clk_init(void) 
	unsigned long sys_rate;

	unsigned long dram_rate;

	unsigned long periph_rate;

	unsigned long pcmi2s_rate;



	xtal_rate = mt7620_get_xtal_rate();
@@ -523,6 +524,7 @@ void __init ralink_clk_init(void) 
			cpu_rate = MHZ(575);

		dram_rate = sys_rate = cpu_rate / 3;

		periph_rate = MHZ(40);

		pcmi2s_rate = MHZ(480);



		ralink_clk_add("10000d00.uartlite", periph_rate);

		ralink_clk_add("10000e00.uartlite", periph_rate);
@@ -534,6 +536,7 @@ void __init ralink_clk_init(void) 
		dram_rate = mt7620_get_dram_rate(pll_rate);

		sys_rate = mt7620_get_sys_rate(cpu_rate);

		periph_rate = mt7620_get_periph_rate(xtal_rate);

		pcmi2s_rate = periph_rate;



		pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),

			 RINT(xtal_rate), RFRAC(xtal_rate),
@@ -555,6 +558,8 @@ void __init ralink_clk_init(void) 
	ralink_clk_add("cpu", cpu_rate);

	ralink_clk_add("10000100.timer", periph_rate);

	ralink_clk_add("10000120.watchdog", periph_rate);

	ralink_clk_add("10000900.i2c", periph_rate);

	ralink_clk_add("10000a00.i2s", pcmi2s_rate);

	ralink_clk_add("10000b00.spi", sys_rate);

	ralink_clk_add("10000b40.spi", sys_rate);

	ralink_clk_add("10000c00.uartlite", periph_rate);

arch/mips/ralink/rt288x.c

+1 −0
Original line number Diff line number Diff line
@@ -75,6 +75,7 @@ void __init ralink_clk_init(void) 
	ralink_clk_add("300100.timer", cpu_rate / 2);

	ralink_clk_add("300120.watchdog", cpu_rate / 2);

	ralink_clk_add("300500.uart", cpu_rate / 2);

	ralink_clk_add("300900.i2c", cpu_rate / 2);

	ralink_clk_add("300c00.uartlite", cpu_rate / 2);

	ralink_clk_add("400000.ethernet", cpu_rate / 2);

	ralink_clk_add("480000.wmac", wmac_rate);

arch/mips/ralink/rt305x.c

+2 −0
Original line number Diff line number Diff line
@@ -200,6 +200,8 @@ void __init ralink_clk_init(void) 


	ralink_clk_add("cpu", cpu_rate);

	ralink_clk_add("sys", sys_rate);

	ralink_clk_add("10000900.i2c", uart_rate);

	ralink_clk_add("10000a00.i2s", uart_rate);

	ralink_clk_add("10000b00.spi", sys_rate);

	ralink_clk_add("10000b40.spi", sys_rate);

	ralink_clk_add("10000100.timer", wdt_rate);

arch/mips/ralink/rt3883.c

+2 −0
Original line number Diff line number Diff line
@@ -108,6 +108,8 @@ void __init ralink_clk_init(void) 
	ralink_clk_add("10000100.timer", sys_rate);

	ralink_clk_add("10000120.watchdog", sys_rate);

	ralink_clk_add("10000500.uart", 40000000);

	ralink_clk_add("10000900.i2c", 40000000);

	ralink_clk_add("10000a00.i2s", 40000000);

	ralink_clk_add("10000b00.spi", sys_rate);

	ralink_clk_add("10000b40.spi", sys_rate);

	ralink_clk_add("10000c00.uartlite", 40000000);