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Commit 2441f877 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Jani Nikula
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drm/i915: Apply WaDisableAsyncFlipPerfMode via LRIs on gen8 



MI_MODE is saved in the logical context so WaDisableAsyncFlipPerfMode
must be applied using LRIs on gen8.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 9cc83020

drivers/gpu/drm/i915/intel_ringbuffer.c

+8 −2
Original line number Diff line number Diff line
@@ -802,6 +802,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) 


	WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);



	/* WaDisableAsyncFlipPerfMode:bdw */

	WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);



	/* WaDisablePartialInstShootdown:bdw */

	/* WaDisableThreadStallDopClockGating:bdw (pre-production) */

	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
@@ -865,6 +868,9 @@ static int chv_init_workarounds(struct intel_engine_cs *ring) 


	WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);



	/* WaDisableAsyncFlipPerfMode:chv */

	WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);



	/* WaDisablePartialInstShootdown:chv */

	/* WaDisableThreadStallDopClockGating:chv */

	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
@@ -1109,9 +1115,9 @@ static int init_render_ring(struct intel_engine_cs *ring) 
	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be

	 * programmed to '1' on all products.

	 *

	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv

	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv

	 */

	if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)

	if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)

		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));



	/* Required for the hardware to program scanline values for waiting */