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Commit 9cc83020 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Jani Nikula
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drm/i915: Set INSTPM_FORCE_ORDERING via LRI on gen8, drop it on gen9+ 



INSTPM is saved in the logical context so we should initialize it using
LRIs on gen8. It actually defaults to 1 starting from HSW, but let's
keep the write around anyway.

Also drop the INSTPM_FORCE_ORDERING setup entirely on gen9+ since it's
now a reserved bit.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 64987fc5

drivers/gpu/drm/i915/intel_ringbuffer.c

+5 −1
Original line number Diff line number Diff line
@@ -800,6 +800,8 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) 
	struct drm_device *dev = ring->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;



	WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);



	/* WaDisablePartialInstShootdown:bdw */

	/* WaDisableThreadStallDopClockGating:bdw (pre-production) */

	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
@@ -861,6 +863,8 @@ static int chv_init_workarounds(struct intel_engine_cs *ring) 
	struct drm_device *dev = ring->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;



	WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);



	/* WaDisablePartialInstShootdown:chv */

	/* WaDisableThreadStallDopClockGating:chv */

	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
@@ -1132,7 +1136,7 @@ static int init_render_ring(struct intel_engine_cs *ring) 
			   _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));

	}



	if (INTEL_INFO(dev)->gen >= 6)

	if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)

		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));



	if (HAS_L3_DPF(dev))