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Commit 1c3dc891 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'hns3-cleanups' 



Yunsheng Lin says:

====================
A few cleanup for hns3 ethernet driver

This patchset contains a few cleanup for hns3 ethernet driver.
No functional change intended.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents c49c777f 1db9b1bf

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c

+8 −8
Original line number Diff line number Diff line
@@ -208,7 +208,7 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 
	 * which will be use for hardware to write back

	 */

	ntc = hw->cmq.csq.next_to_use;

	opcode = desc[0].opcode;

	opcode = le16_to_cpu(desc[0].opcode);

	while (handle < num) {

		desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];

		*desc_to_use = desc[handle];
@@ -225,7 +225,7 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 
	 * If the command is sync, wait for the firmware to write back,

	 * if multi descriptors to be sent, use the first one to check

	 */

	if (HCLGE_SEND_SYNC(desc->flag)) {

	if (HCLGE_SEND_SYNC(le16_to_cpu(desc->flag))) {

		do {

			if (hclge_cmd_csq_done(hw))

				break;
@@ -244,9 +244,9 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 
			pr_debug("Get cmd desc:\n");



			if (likely(!hclge_is_special_opcode(opcode)))

				desc_ret = desc[handle].retval;

				desc_ret = le16_to_cpu(desc[handle].retval);

			else

				desc_ret = desc[0].retval;

				desc_ret = le16_to_cpu(desc[0].retval);



			if ((enum hclge_cmd_return_status)desc_ret ==

			    HCLGE_CMD_EXEC_SUCCESS)
@@ -276,15 +276,15 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 
	return retval;

}



enum hclge_cmd_status hclge_cmd_query_firmware_version(struct hclge_hw *hw,

						       u32 *version)

static enum hclge_cmd_status hclge_cmd_query_firmware_version(

		struct hclge_hw *hw, u32 *version)

{

	struct hclge_query_version *resp;

	struct hclge_query_version_cmd *resp;

	struct hclge_desc desc;

	int ret;



	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FW_VER, 1);

	resp = (struct hclge_query_version *)desc.data;

	resp = (struct hclge_query_version_cmd *)desc.data;



	ret = hclge_cmd_send(hw, &desc, 1);

	if (!ret)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

+65 −65
Original line number Diff line number Diff line
@@ -221,12 +221,12 @@ enum hclge_opcode_type { 
#define HCLGE_RCB_INIT_QUERY_TIMEOUT	10

#define HCLGE_RCB_INIT_FLAG_EN_B	0

#define HCLGE_RCB_INIT_FLAG_FINI_B	8

struct hclge_config_rcb_init {

struct hclge_config_rcb_init_cmd {

	__le16 rcb_init_flag;

	u8 rsv[22];

};



struct hclge_tqp_map {

struct hclge_tqp_map_cmd {

	__le16 tqp_id;	/* Absolute tqp id for in this pf */

	u8 tqp_vf;	/* VF id */

#define HCLGE_TQP_MAP_TYPE_PF		0
@@ -246,15 +246,15 @@ enum hclge_int_type { 
	HCLGE_INT_EVENT,

};



struct hclge_ctrl_vector_chain {

struct hclge_ctrl_vector_chain_cmd {

	u8 int_vector_id;

	u8 int_cause_num;

#define HCLGE_INT_TYPE_S	0

#define HCLGE_INT_TYPE_M	0x3

#define HCLGE_INT_TYPE_M	GENMASK(1, 0)

#define HCLGE_TQP_ID_S		2

#define HCLGE_TQP_ID_M		(0x7ff << HCLGE_TQP_ID_S)

#define HCLGE_TQP_ID_M		GENMASK(12, 2)

#define HCLGE_INT_GL_IDX_S	13

#define HCLGE_INT_GL_IDX_M	(0x3 << HCLGE_INT_GL_IDX_S)

#define HCLGE_INT_GL_IDX_M	GENMASK(14, 13)

	__le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];

	u8 vfid;

	u8 rsv;
@@ -263,18 +263,18 @@ struct hclge_ctrl_vector_chain { 
#define HCLGE_TC_NUM		8

#define HCLGE_TC0_PRI_BUF_EN_B	15 /* Bit 15 indicate enable or not */

#define HCLGE_BUF_UNIT_S	7  /* Buf size is united by 128 bytes */

struct hclge_tx_buff_alloc {

struct hclge_tx_buff_alloc_cmd {

	__le16 tx_pkt_buff[HCLGE_TC_NUM];

	u8 tx_buff_rsv[8];

};



struct hclge_rx_priv_buff {

struct hclge_rx_priv_buff_cmd {

	__le16 buf_num[HCLGE_TC_NUM];

	__le16 shared_buf;

	u8 rsv[6];

};



struct hclge_query_version {

struct hclge_query_version_cmd {

	__le32 firmware;

	__le32 firmware_rsv[5];

};
@@ -328,14 +328,14 @@ struct hclge_pkt_buf_alloc { 
};



#define HCLGE_RX_COM_WL_EN_B	15

struct hclge_rx_com_wl_buf {

struct hclge_rx_com_wl_buf_cmd {

	__le16 high_wl;

	__le16 low_wl;

	u8 rsv[20];

};



#define HCLGE_RX_PKT_EN_B	15

struct hclge_rx_pkt_buf {

struct hclge_rx_pkt_buf_cmd {

	__le16 high_pkt;

	__le16 low_pkt;

	u8 rsv[20];
@@ -348,7 +348,7 @@ struct hclge_rx_pkt_buf { 
#define HCLGE_PF_MAC_NUM_MASK	0x3

#define HCLGE_PF_STATE_MAIN	BIT(HCLGE_PF_STATE_MAIN_B)

#define HCLGE_PF_STATE_DONE	BIT(HCLGE_PF_STATE_DONE_B)

struct hclge_func_status {

struct hclge_func_status_cmd {

	__le32  vf_rst_state[4];

	u8 pf_state;

	u8 mac_id;
@@ -359,7 +359,7 @@ struct hclge_func_status { 
	u8 rsv[2];

};



struct hclge_pf_res {

struct hclge_pf_res_cmd {

	__le16 tqp_num;

	__le16 buf_size;

	__le16 msixcap_localid_ba_nic;
@@ -372,30 +372,30 @@ struct hclge_pf_res { 
};



#define HCLGE_CFG_OFFSET_S	0

#define HCLGE_CFG_OFFSET_M	0xfffff /* Byte (8-10.3) */

#define HCLGE_CFG_OFFSET_M	GENMASK(19, 0)

#define HCLGE_CFG_RD_LEN_S	24

#define HCLGE_CFG_RD_LEN_M	(0xf << HCLGE_CFG_RD_LEN_S)

#define HCLGE_CFG_RD_LEN_M	GENMASK(27, 24)

#define HCLGE_CFG_RD_LEN_BYTES	16

#define HCLGE_CFG_RD_LEN_UNIT	4



#define HCLGE_CFG_VMDQ_S	0

#define HCLGE_CFG_VMDQ_M	(0xff << HCLGE_CFG_VMDQ_S)

#define HCLGE_CFG_VMDQ_M	GENMASK(7, 0)

#define HCLGE_CFG_TC_NUM_S	8

#define HCLGE_CFG_TC_NUM_M	(0xff << HCLGE_CFG_TC_NUM_S)

#define HCLGE_CFG_TC_NUM_M	GENMASK(15, 8)

#define HCLGE_CFG_TQP_DESC_N_S	16

#define HCLGE_CFG_TQP_DESC_N_M	(0xffff << HCLGE_CFG_TQP_DESC_N_S)

#define HCLGE_CFG_TQP_DESC_N_M	GENMASK(31, 16)

#define HCLGE_CFG_PHY_ADDR_S	0

#define HCLGE_CFG_PHY_ADDR_M	(0x1f << HCLGE_CFG_PHY_ADDR_S)

#define HCLGE_CFG_PHY_ADDR_M	GENMASK(4, 0)

#define HCLGE_CFG_MEDIA_TP_S	8

#define HCLGE_CFG_MEDIA_TP_M	(0xff << HCLGE_CFG_MEDIA_TP_S)

#define HCLGE_CFG_MEDIA_TP_M	GENMASK(15, 8)

#define HCLGE_CFG_RX_BUF_LEN_S	16

#define HCLGE_CFG_RX_BUF_LEN_M	(0xffff << HCLGE_CFG_RX_BUF_LEN_S)

#define HCLGE_CFG_RX_BUF_LEN_M	GENMASK(31, 16)

#define HCLGE_CFG_MAC_ADDR_H_S	0

#define HCLGE_CFG_MAC_ADDR_H_M	(0xffff << HCLGE_CFG_MAC_ADDR_H_S)

#define HCLGE_CFG_MAC_ADDR_H_M	GENMASK(15, 0)

#define HCLGE_CFG_DEFAULT_SPEED_S	16

#define HCLGE_CFG_DEFAULT_SPEED_M	(0xff << HCLGE_CFG_DEFAULT_SPEED_S)

#define HCLGE_CFG_DEFAULT_SPEED_M	GENMASK(23, 16)



struct hclge_cfg_param {

struct hclge_cfg_param_cmd {

	__le32 offset;

	__le32 rsv;

	__le32 param[4];
@@ -405,7 +405,7 @@ struct hclge_cfg_param { 
#define HCLGE_DESC_NUM		0x40



#define HCLGE_ALLOC_VALID_B	0

struct hclge_vf_num {

struct hclge_vf_num_cmd {

	u8 alloc_valid;

	u8 rsv[23];

};
@@ -413,13 +413,13 @@ struct hclge_vf_num { 
#define HCLGE_RSS_DEFAULT_OUTPORT_B	4

#define HCLGE_RSS_HASH_KEY_OFFSET_B	4

#define HCLGE_RSS_HASH_KEY_NUM		16

struct hclge_rss_config {

struct hclge_rss_config_cmd {

	u8 hash_config;

	u8 rsv[7];

	u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];

};



struct hclge_rss_input_tuple {

struct hclge_rss_input_tuple_cmd {

	u8 ipv4_tcp_en;

	u8 ipv4_udp_en;

	u8 ipv4_sctp_en;
@@ -433,26 +433,26 @@ struct hclge_rss_input_tuple { 


#define HCLGE_RSS_CFG_TBL_SIZE	16



struct hclge_rss_indirection_table {

	u16 start_table_index;

	u16 rss_set_bitmap;

struct hclge_rss_indirection_table_cmd {

	__le16 start_table_index;

	__le16 rss_set_bitmap;

	u8 rsv[4];

	u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE];

};



#define HCLGE_RSS_TC_OFFSET_S		0

#define HCLGE_RSS_TC_OFFSET_M		(0x3ff << HCLGE_RSS_TC_OFFSET_S)

#define HCLGE_RSS_TC_OFFSET_M		GENMASK(9, 0)

#define HCLGE_RSS_TC_SIZE_S		12

#define HCLGE_RSS_TC_SIZE_M		(0x7 << HCLGE_RSS_TC_SIZE_S)

#define HCLGE_RSS_TC_SIZE_M		GENMASK(14, 12)

#define HCLGE_RSS_TC_VALID_B		15

struct hclge_rss_tc_mode {

	u16 rss_tc_mode[HCLGE_MAX_TC_NUM];

struct hclge_rss_tc_mode_cmd {

	__le16 rss_tc_mode[HCLGE_MAX_TC_NUM];

	u8 rsv[8];

};



#define HCLGE_LINK_STS_B	0

#define HCLGE_LINK_STATUS	BIT(HCLGE_LINK_STS_B)

struct hclge_link_status {

struct hclge_link_status_cmd {

	u8 status;

	u8 rsv[23];

};
@@ -467,7 +467,7 @@ struct hclge_promisc_param { 
#define HCLGE_PROMISC_EN_UC	0x1

#define HCLGE_PROMISC_EN_MC	0x2

#define HCLGE_PROMISC_EN_BC	0x4

struct hclge_promisc_cfg {

struct hclge_promisc_cfg_cmd {

	u8 flag;

	u8 vf_id;

	__le16 rsv0;
@@ -495,18 +495,18 @@ enum hclge_promisc_type { 
#define HCLGE_MAC_TX_UNDER_MIN_ERR_B		21

#define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B	22



struct hclge_config_mac_mode {

struct hclge_config_mac_mode_cmd {

	__le32 txrx_pad_fcs_loop_en;

	u8 rsv[20];

};



#define HCLGE_CFG_SPEED_S		0

#define HCLGE_CFG_SPEED_M		(0x3f << HCLGE_CFG_SPEED_S)

#define HCLGE_CFG_SPEED_M		GENMASK(5, 0)



#define HCLGE_CFG_DUPLEX_B		7

#define HCLGE_CFG_DUPLEX_M		BIT(HCLGE_CFG_DUPLEX_B)



struct hclge_config_mac_speed_dup {

struct hclge_config_mac_speed_dup_cmd {

	u8 speed_dup;



#define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B	0
@@ -518,17 +518,17 @@ struct hclge_config_mac_speed_dup { 
#define HCLGE_QUERY_AN_B		0

#define HCLGE_QUERY_DUPLEX_B		2



#define HCLGE_QUERY_SPEED_M		(0x1f << HCLGE_QUERY_SPEED_S)

#define HCLGE_QUERY_SPEED_M		GENMASK(4, 0)

#define HCLGE_QUERY_AN_M		BIT(HCLGE_QUERY_AN_B)

#define HCLGE_QUERY_DUPLEX_M		BIT(HCLGE_QUERY_DUPLEX_B)



struct hclge_query_an_speed_dup {

struct hclge_query_an_speed_dup_cmd {

	u8 an_syn_dup_speed;

	u8 pause;

	u8 rsv[23];

};



#define HCLGE_RING_ID_MASK		0x3ff

#define HCLGE_RING_ID_MASK		GENMASK(9, 0)

#define HCLGE_TQP_ENABLE_B		0



#define HCLGE_MAC_CFG_AN_EN_B		0
@@ -539,7 +539,7 @@ struct hclge_query_an_speed_dup { 


#define HCLGE_MAC_CFG_AN_EN	BIT(HCLGE_MAC_CFG_AN_EN_B)



struct hclge_config_auto_neg {

struct hclge_config_auto_neg_cmd {

	__le32  cfg_an_cmd_flag;

	u8      rsv[20];

};
@@ -548,7 +548,7 @@ struct hclge_config_auto_neg { 
#define HCLGE_MAC_MAX_MTU		9728

#define HCLGE_MAC_UPLINK_PORT		0x100



struct hclge_config_max_frm_size {

struct hclge_config_max_frm_size_cmd {

	__le16  max_frm_size;

	u8      rsv[22];

};
@@ -565,10 +565,10 @@ enum hclge_mac_vlan_tbl_opcode { 
#define HCLGE_MAC_EPORT_SW_EN_B		0xc

#define HCLGE_MAC_EPORT_TYPE_B		0xb

#define HCLGE_MAC_EPORT_VFID_S		0x3

#define HCLGE_MAC_EPORT_VFID_M		(0xff << HCLGE_MAC_EPORT_VFID_S)

#define HCLGE_MAC_EPORT_VFID_M		GENMASK(10, 3)

#define HCLGE_MAC_EPORT_PFID_S		0x0

#define HCLGE_MAC_EPORT_PFID_M		(0x7 << HCLGE_MAC_EPORT_PFID_S)

struct hclge_mac_vlan_tbl_entry {

#define HCLGE_MAC_EPORT_PFID_M		GENMASK(2, 0)

struct hclge_mac_vlan_tbl_entry_cmd {

	u8	flags;

	u8      resp_code;

	__le16  vlan_tag;
@@ -583,15 +583,15 @@ struct hclge_mac_vlan_tbl_entry { 
};



#define HCLGE_CFG_MTA_MAC_SEL_S		0x0

#define HCLGE_CFG_MTA_MAC_SEL_M		(0x3 << HCLGE_CFG_MTA_MAC_SEL_S)

#define HCLGE_CFG_MTA_MAC_SEL_M		GENMASK(1, 0)

#define HCLGE_CFG_MTA_MAC_EN_B		0x7

struct hclge_mta_filter_mode {

struct hclge_mta_filter_mode_cmd {

	u8	dmac_sel_en; /* Use lowest 2 bit as sel_mode, bit 7 as enable */

	u8      rsv[23];

};



#define HCLGE_CFG_FUNC_MTA_ACCEPT_B	0x0

struct hclge_cfg_func_mta_filter {

struct hclge_cfg_func_mta_filter_cmd {

	u8	accept; /* Only used lowest 1 bit */

	u8      function_id;

	u8      rsv[22];
@@ -599,14 +599,14 @@ struct hclge_cfg_func_mta_filter { 


#define HCLGE_CFG_MTA_ITEM_ACCEPT_B	0x0

#define HCLGE_CFG_MTA_ITEM_IDX_S	0x0

#define HCLGE_CFG_MTA_ITEM_IDX_M	(0xfff << HCLGE_CFG_MTA_ITEM_IDX_S)

struct hclge_cfg_func_mta_item {

	u16	item_idx; /* Only used lowest 12 bit */

#define HCLGE_CFG_MTA_ITEM_IDX_M	GENMASK(11, 0)

struct hclge_cfg_func_mta_item_cmd {

	__le16	item_idx; /* Only used lowest 12 bit */

	u8      accept;   /* Only used lowest 1 bit */

	u8      rsv[21];

};



struct hclge_mac_vlan_add {

struct hclge_mac_vlan_add_cmd {

	__le16  flags;

	__le16  mac_addr_hi16;

	__le32  mac_addr_lo32;
@@ -619,7 +619,7 @@ struct hclge_mac_vlan_add { 
};



#define HNS3_MAC_VLAN_CFG_FLAG_BIT 0

struct hclge_mac_vlan_remove {

struct hclge_mac_vlan_remove_cmd {

	__le16  flags;

	__le16  mac_addr_hi16;

	__le32  mac_addr_lo32;
@@ -631,21 +631,21 @@ struct hclge_mac_vlan_remove { 
	u8      rsv[4];

};



struct hclge_vlan_filter_ctrl {

struct hclge_vlan_filter_ctrl_cmd {

	u8 vlan_type;

	u8 vlan_fe;

	u8 rsv[22];

};



struct hclge_vlan_filter_pf_cfg {

struct hclge_vlan_filter_pf_cfg_cmd {

	u8 vlan_offset;

	u8 vlan_cfg;

	u8 rsv[2];

	u8 vlan_offset_bitmap[20];

};



struct hclge_vlan_filter_vf_cfg {

	u16 vlan_id;

struct hclge_vlan_filter_vf_cfg_cmd {

	__le16 vlan_id;

	u8  resp_code;

	u8  rsv;

	u8  vlan_cfg;
@@ -653,14 +653,14 @@ struct hclge_vlan_filter_vf_cfg { 
	u8  vf_bitmap[16];

};



struct hclge_cfg_com_tqp_queue {

struct hclge_cfg_com_tqp_queue_cmd {

	__le16 tqp_id;

	__le16 stream_id;

	u8 enable;

	u8 rsv[19];

};



struct hclge_cfg_tx_queue_pointer {

struct hclge_cfg_tx_queue_pointer_cmd {

	__le16 tqp_id;

	__le16 tx_tail;

	__le16 tx_head;
@@ -670,12 +670,12 @@ struct hclge_cfg_tx_queue_pointer { 
};



#define HCLGE_TSO_MSS_MIN_S	0

#define HCLGE_TSO_MSS_MIN_M	(0x3FFF << HCLGE_TSO_MSS_MIN_S)

#define HCLGE_TSO_MSS_MIN_M	GENMASK(13, 0)



#define HCLGE_TSO_MSS_MAX_S	16

#define HCLGE_TSO_MSS_MAX_M	(0x3FFF << HCLGE_TSO_MSS_MAX_S)

#define HCLGE_TSO_MSS_MAX_M	GENMASK(29, 16)



struct hclge_cfg_tso_status {

struct hclge_cfg_tso_status_cmd {

	__le16 tso_mss_min;

	__le16 tso_mss_max;

	u8 rsv[20];
@@ -685,7 +685,7 @@ struct hclge_cfg_tso_status { 
#define HCLGE_TSO_MSS_MAX	9668



#define HCLGE_TQP_RESET_B	0

struct hclge_reset_tqp_queue {

struct hclge_reset_tqp_queue_cmd {

	__le16 tqp_id;

	u8 reset_req;

	u8 ready_to_reset;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+208 −177

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

+2 −2
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ 
#define HCLGE_VECTOR_VF_OFFSET		0x100000



#define HCLGE_RSS_IND_TBL_SIZE		512

#define HCLGE_RSS_SET_BITMAP_MSK	0xffff

#define HCLGE_RSS_SET_BITMAP_MSK	GENMASK(15, 0)

#define HCLGE_RSS_KEY_SIZE		40

#define HCLGE_RSS_HASH_ALGO_TOEPLITZ	0

#define HCLGE_RSS_HASH_ALGO_SIMPLE	1
@@ -65,7 +65,7 @@ 
#define HCLGE_PHY_CSS_REG		17



#define HCLGE_PHY_MDIX_CTRL_S		(5)

#define HCLGE_PHY_MDIX_CTRL_M		(3 << HCLGE_PHY_MDIX_CTRL_S)

#define HCLGE_PHY_MDIX_CTRL_M		GENMASK(6, 5)



#define HCLGE_PHY_MDIX_STATUS_B	(6)

#define HCLGE_PHY_SPEED_DUP_RESOLVE_B	(11)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c

+16 −10
Original line number Diff line number Diff line
@@ -283,6 +283,7 @@ static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev, 
	struct hclge_pg_shapping_cmd *shap_cfg_cmd;

	enum hclge_opcode_type opcode;

	struct hclge_desc desc;

	u32 shapping_para = 0;



	opcode = bucket ? HCLGE_OPC_TM_PG_P_SHAPPING :

		HCLGE_OPC_TM_PG_C_SHAPPING;
@@ -292,11 +293,13 @@ static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev, 


	shap_cfg_cmd->pg_id = pg_id;



	hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, IR_B, ir_b);

	hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, IR_U, ir_u);

	hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, IR_S, ir_s);

	hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, BS_B, bs_b);

	hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, BS_S, bs_s);

	hclge_tm_set_field(shapping_para, IR_B, ir_b);

	hclge_tm_set_field(shapping_para, IR_U, ir_u);

	hclge_tm_set_field(shapping_para, IR_S, ir_s);

	hclge_tm_set_field(shapping_para, BS_B, bs_b);

	hclge_tm_set_field(shapping_para, BS_S, bs_s);



	shap_cfg_cmd->pg_shapping_para = cpu_to_le32(shapping_para);



	return hclge_cmd_send(&hdev->hw, &desc, 1);

}
@@ -337,6 +340,7 @@ static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev, 
	struct hclge_pri_shapping_cmd *shap_cfg_cmd;

	enum hclge_opcode_type opcode;

	struct hclge_desc desc;

	u32 shapping_para = 0;



	opcode = bucket ? HCLGE_OPC_TM_PRI_P_SHAPPING :

		HCLGE_OPC_TM_PRI_C_SHAPPING;
@@ -347,11 +351,13 @@ static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev, 


	shap_cfg_cmd->pri_id = pri_id;



	hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, IR_B, ir_b);

	hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, IR_U, ir_u);

	hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, IR_S, ir_s);

	hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, BS_B, bs_b);

	hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, BS_S, bs_s);

	hclge_tm_set_field(shapping_para, IR_B, ir_b);

	hclge_tm_set_field(shapping_para, IR_U, ir_u);

	hclge_tm_set_field(shapping_para, IR_S, ir_s);

	hclge_tm_set_field(shapping_para, BS_B, bs_b);

	hclge_tm_set_field(shapping_para, BS_S, bs_s);



	shap_cfg_cmd->pri_shapping_para = cpu_to_le32(shapping_para);



	return hclge_cmd_send(&hdev->hw, &desc, 1);

}