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Commit 1b85066b authored by Jordan Justen's avatar Jordan Justen Committed by Daniel Vetter
Browse files

drm/i915: Add Haswell CS GPR registers to whitelist 



This is needed for the Mesa Vulkan driver on Haswell.

Signed-off-by: default avatarJordan Justen <jordan.l.justen@intel.com>
Reviewed-by: default avatarFrancisco Jerez <currojerez@riseup.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1457335830-30923-5-git-send-email-jordan.l.justen@intel.com
parent 99c5aeca

drivers/gpu/drm/i915/i915_cmd_parser.c

+16 −0
Original line number Diff line number Diff line
@@ -475,6 +475,22 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = { 
};



static const struct drm_i915_reg_descriptor hsw_render_regs[] = {

	REG64_IDX(HSW_CS_GPR, 0),

	REG64_IDX(HSW_CS_GPR, 1),

	REG64_IDX(HSW_CS_GPR, 2),

	REG64_IDX(HSW_CS_GPR, 3),

	REG64_IDX(HSW_CS_GPR, 4),

	REG64_IDX(HSW_CS_GPR, 5),

	REG64_IDX(HSW_CS_GPR, 6),

	REG64_IDX(HSW_CS_GPR, 7),

	REG64_IDX(HSW_CS_GPR, 8),

	REG64_IDX(HSW_CS_GPR, 9),

	REG64_IDX(HSW_CS_GPR, 10),

	REG64_IDX(HSW_CS_GPR, 11),

	REG64_IDX(HSW_CS_GPR, 12),

	REG64_IDX(HSW_CS_GPR, 13),

	REG64_IDX(HSW_CS_GPR, 14),

	REG64_IDX(HSW_CS_GPR, 15),

	REG32(HSW_SCRATCH1,

	      .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,

	      .value = 0),

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -588,6 +588,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define GEN7_GPGPU_DISPATCHDIMY         _MMIO(0x2504)

#define GEN7_GPGPU_DISPATCHDIMZ         _MMIO(0x2508)



/* There are the 16 64-bit CS General Purpose Registers */

#define HSW_CS_GPR(n)                   _MMIO(0x2600 + (n) * 8)

#define HSW_CS_GPR_UDW(n)               _MMIO(0x2600 + (n) * 8 + 4)



#define OACONTROL _MMIO(0x2360)



#define _GEN7_PIPEA_DE_LOAD_SL	0x70068