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Commit 99c5aeca authored by Jordan Justen's avatar Jordan Justen Committed by Daniel Vetter
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drm/i915: Move Haswell registers to separate whitelist table 



Now that we can whitelist registers only on Haswell, move HSW_SCRATCH1
and HSW_ROW_CHICKEN3 into a separate Haswell only table.

Signed-off-by: default avatarJordan Justen <jordan.l.justen@intel.com>
Cc: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: default avatarFrancisco Jerez <currojerez@riseup.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1457335830-30923-4-git-send-email-jordan.l.justen@intel.com
parent 361b027b

drivers/gpu/drm/i915/i915_cmd_parser.c

+4 −0
Original line number Diff line number Diff line
@@ -472,6 +472,9 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = { 
	REG32(GEN7_L3SQCREG1),

	REG32(GEN7_L3CNTLREG2),

	REG32(GEN7_L3CNTLREG3),

};



static const struct drm_i915_reg_descriptor hsw_render_regs[] = {

	REG32(HSW_SCRATCH1,

	      .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,

	      .value = 0),
@@ -519,6 +522,7 @@ static const struct drm_i915_reg_table ivb_blt_reg_tables[] = { 


static const struct drm_i915_reg_table hsw_render_reg_tables[] = {

	{ gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },

	{ hsw_render_regs, ARRAY_SIZE(hsw_render_regs), false },

	{ hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },

};