Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 16b5b092 authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge branch 'pm-tools' 

* pm-tools:
  cpupower: Add support for new AMD family 0x17
  cpupower: Fix bug where return value was not used
  tools/power turbostat: update version number
  tools/power turbostat: decode MSR_IA32_MISC_ENABLE only on Intel
  tools/power turbostat: stop migrating, unless '-m'
  tools/power turbostat: if  --debug, print sampling overhead
  tools/power turbostat: hide SKL counters, when not requested
  intel_pstate: use updated msr-index.h HWP.EPP values
  tools/power x86_energy_perf_policy: support HWP.EPP
  x86: msr-index.h: fix shifts to ULL results in HWP macros.
  x86: msr-index.h: define HWP.EPP values
  x86: msr-index.h: define EPB mid-points
parents 875aabf5 902bef73

arch/x86/include/asm/msr-index.h

+12 −6
Original line number Diff line number Diff line
@@ -249,9 +249,13 @@ 
#define HWP_MIN_PERF(x) 		(x & 0xff)

#define HWP_MAX_PERF(x) 		((x & 0xff) << 8)

#define HWP_DESIRED_PERF(x)		((x & 0xff) << 16)

#define HWP_ENERGY_PERF_PREFERENCE(x)	((x & 0xff) << 24)

#define HWP_ACTIVITY_WINDOW(x)		((x & 0xff3) << 32)

#define HWP_PACKAGE_CONTROL(x)		((x & 0x1) << 42)

#define HWP_ENERGY_PERF_PREFERENCE(x)	(((unsigned long long) x & 0xff) << 24)

#define HWP_EPP_PERFORMANCE		0x00

#define HWP_EPP_BALANCE_PERFORMANCE	0x80

#define HWP_EPP_BALANCE_POWERSAVE	0xC0

#define HWP_EPP_POWERSAVE		0xFF

#define HWP_ACTIVITY_WINDOW(x)		((unsigned long long)(x & 0xff3) << 32)

#define HWP_PACKAGE_CONTROL(x)		((unsigned long long)(x & 0x1) << 42)



/* IA32_HWP_STATUS */

#define HWP_GUARANTEED_CHANGE(x)	(x & 0x1)
@@ -475,7 +479,9 @@ 


#define MSR_IA32_ENERGY_PERF_BIAS	0x000001b0

#define ENERGY_PERF_BIAS_PERFORMANCE		0

#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE	4

#define ENERGY_PERF_BIAS_NORMAL			6

#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE	8

#define ENERGY_PERF_BIAS_POWERSAVE		15



#define MSR_IA32_PACKAGE_THERM_STATUS		0x000001b1

drivers/cpufreq/intel_pstate.c

+15 −19
Original line number Diff line number Diff line
@@ -653,6 +653,12 @@ static const char * const energy_perf_strings[] = { 
	"power",

	NULL

};

static const unsigned int epp_values[] = {

	HWP_EPP_PERFORMANCE,

	HWP_EPP_BALANCE_PERFORMANCE,

	HWP_EPP_BALANCE_POWERSAVE,

	HWP_EPP_POWERSAVE

};



static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)

{
@@ -664,17 +670,14 @@ static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data) 
		return epp;



	if (static_cpu_has(X86_FEATURE_HWP_EPP)) {

		/*

		 * Range:

		 *	0x00-0x3F	:	Performance

		 *	0x40-0x7F	:	Balance performance

		 *	0x80-0xBF	:	Balance power

		 *	0xC0-0xFF	:	Power

		 * The EPP is a 8 bit value, but our ranges restrict the

		 * value which can be set. Here only using top two bits

		 * effectively.

		 */

		index = (epp >> 6) + 1;

		if (epp == HWP_EPP_PERFORMANCE)

			return 1;

		if (epp <= HWP_EPP_BALANCE_PERFORMANCE)

			return 2;

		if (epp <= HWP_EPP_BALANCE_POWERSAVE)

			return 3;

		else

			return 4;

	} else if (static_cpu_has(X86_FEATURE_EPB)) {

		/*

		 * Range:
@@ -712,15 +715,8 @@ static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 


		value &= ~GENMASK_ULL(31, 24);



		/*

		 * If epp is not default, convert from index into

		 * energy_perf_strings to epp value, by shifting 6

		 * bits left to use only top two bits in epp.

		 * The resultant epp need to shifted by 24 bits to

		 * epp position in MSR_HWP_REQUEST.

		 */

		if (epp == -EINVAL)

			epp = (pref_index - 1) << 6;

			epp = epp_values[pref_index - 1];



		value |= (u64)epp << 24;

		ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);

tools/power/cpupower/utils/helpers/amd.c

+23 −8
Original line number Diff line number Diff line
@@ -26,6 +26,15 @@ union msr_pstate { 
		unsigned res3:21;

		unsigned en:1;

	} bits;

	struct {

		unsigned fid:8;

		unsigned did:6;

		unsigned vid:8;

		unsigned iddval:8;

		unsigned idddiv:2;

		unsigned res1:30;

		unsigned en:1;

	} fam17h_bits;

	unsigned long long val;

};
@@ -35,6 +44,8 @@ static int get_did(int family, union msr_pstate pstate) 


	if (family == 0x12)

		t = pstate.val & 0xf;

	else if (family == 0x17)

		t = pstate.fam17h_bits.did;

	else

		t = pstate.bits.did;
@@ -44,16 +55,20 @@ static int get_did(int family, union msr_pstate pstate) 
static int get_cof(int family, union msr_pstate pstate)

{

	int t;

	int fid, did;

	int fid, did, cof;



	did = get_did(family, pstate);



	if (family == 0x17) {

		fid = pstate.fam17h_bits.fid;

		cof = 200 * fid / did;

	} else {

		t = 0x10;

		fid = pstate.bits.fid;

		if (family == 0x11)

			t = 0x8;



	return (100 * (fid + t)) >> did;

		cof = (100 * (fid + t)) >> did;

	}

	return cof;

}



/* Needs:

tools/power/cpupower/utils/helpers/helpers.h

+2 −0
Original line number Diff line number Diff line
@@ -70,6 +70,8 @@ enum cpupower_cpu_vendor {X86_VENDOR_UNKNOWN = 0, X86_VENDOR_INTEL, 
#define CPUPOWER_CAP_IS_SNB		0x00000020

#define CPUPOWER_CAP_INTEL_IDA		0x00000040



#define CPUPOWER_AMD_CPBDIS		0x02000000



#define MAX_HW_PSTATES 10



struct cpupower_cpu_info {

tools/power/cpupower/utils/helpers/misc.c

+19 −4
Original line number Diff line number Diff line
@@ -2,11 +2,14 @@ 


#include "helpers/helpers.h"



#define MSR_AMD_HWCR	0xc0010015



int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active,

			int *states)

{

	struct cpupower_cpu_info cpu_info;

	int ret;

	unsigned long long val;



	*support = *active = *states = 0;
@@ -16,10 +19,22 @@ int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active, 


	if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_CBP) {

		*support = 1;

		amd_pci_get_num_boost_states(active, states);

		if (ret <= 0)



		/* AMD Family 0x17 does not utilize PCI D18F4 like prior

		 * families and has no fixed discrete boost states but

		 * has Hardware determined variable increments instead.

		 */



		if (cpu_info.family == 0x17) {

			if (!read_msr(cpu, MSR_AMD_HWCR, &val)) {

				if (!(val & CPUPOWER_AMD_CPBDIS))

					*active = 1;

			}

		} else {

			ret = amd_pci_get_num_boost_states(active, states);

			if (ret)

				return ret;

		*support = 1;

		}

	} else if (cpupower_cpu_info.caps & CPUPOWER_CAP_INTEL_IDA)

		*support = *active = 1;

	return 0;