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Commit 159f5ae7 authored by Leilk Liu's avatar Leilk Liu Committed by Matthias Brugger
Browse files

arm: dts: mt2701: Add spi device node 



Add spi device node for MT2701.

Signed-off-by: default avatarLeilk Liu <leilk.liu@mediatek.com>
Signed-off-by: default avatarErin Lo <erin.lo@mediatek.com>
Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent f3cba0f4

arch/arm/boot/dts/mt2701-evb.dts

+50 −0
Original line number Diff line number Diff line
@@ -24,6 +24,56 @@ 
	};

};



&pio {

	spi_pins_a: spi0@0 {

		pins_spi {

			pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,

				 <MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK>,

				 <MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI>,

				 <MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO>;

			bias-disable;

		};

	};



	spi_pins_b: spi1@0 {

		pins_spi {

			pinmux = <MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS>,

				 <MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI>,

				 <MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO>,

				 <MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK>;

			bias-disable;

		};

	};



	spi_pins_c: spi2@0 {

		pins_spi {

			pinmux = <MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS>,

				 <MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI>,

				 <MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO>,

				 <MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK>;

			bias-disable;

		};

	};

};



&spi0 {

	pinctrl-names = "default";

	pinctrl-0 = <&spi_pins_a>;

	status = "disabled";

};



&spi1 {

	pinctrl-names = "default";

	pinctrl-0 = <&spi_pins_b>;

	status = "disabled";

};



&spi2 {

	pinctrl-names = "default";

	pinctrl-0 = <&spi_pins_c>;

	status = "disabled";

};



&uart0 {

	status = "okay";

};

arch/arm/boot/dts/mt2701.dtsi

+39 −0
Original line number Diff line number Diff line
@@ -247,6 +247,45 @@ 
		status = "disabled";

	};



	spi0: spi@1100a000 {

		compatible = "mediatek,mt2701-spi";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0 0x1100a000 0 0x100>;

		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,

			 <&topckgen CLK_TOP_SPI0_SEL>,

			 <&pericfg CLK_PERI_SPI0>;

		clock-names = "parent-clk", "sel-clk", "spi-clk";

		status = "disabled";

	};



	spi1: spi@11016000 {

		compatible = "mediatek,mt2701-spi";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0 0x11016000 0 0x100>;

		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,

			 <&topckgen CLK_TOP_SPI1_SEL>,

			 <&pericfg CLK_PERI_SPI1>;

		clock-names = "parent-clk", "sel-clk", "spi-clk";

		status = "disabled";

	};



	spi2: spi@11017000 {

		compatible = "mediatek,mt2701-spi";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0 0x11017000 0 0x1000>;

		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,

			 <&topckgen CLK_TOP_SPI2_SEL>,

			 <&pericfg CLK_PERI_SPI2>;

		clock-names = "parent-clk", "sel-clk", "spi-clk";

		status = "disabled";

	};



	mmsys: syscon@14000000 {

		compatible = "mediatek,mt2701-mmsys", "syscon";

		reg = <0 0x14000000 0 0x1000>;