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Commit f3cba0f4 authored by Honghui Zhang's avatar Honghui Zhang Committed by Matthias Brugger
Browse files

ARM: dts: mt2701: add iommu/smi dtsi node for mt2701 



Add the dtsi node of iommu and smi for mt2701.

Signed-off-by: default avatarHonghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 571b9589

arch/arm/boot/dts/mt2701.dtsi

+50 −0
Original line number Original line Diff line number Diff line
@@ -161,6 +161,16 @@ 
			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;

			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;

	};

	};





	smi_common: smi@1000c000 {

		compatible = "mediatek,mt2701-smi-common";

		reg = <0 0x1000c000 0 0x1000>;

		clocks = <&infracfg CLK_INFRA_SMI>,

			 <&mmsys CLK_MM_SMI_COMMON>,

			 <&infracfg CLK_INFRA_SMI>;

		clock-names = "apb", "smi", "async";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;

	};



	sysirq: interrupt-controller@10200100 {

	sysirq: interrupt-controller@10200100 {

		compatible = "mediatek,mt2701-sysirq",

		compatible = "mediatek,mt2701-sysirq",

			     "mediatek,mt6577-sysirq";

			     "mediatek,mt6577-sysirq";
@@ -170,6 +180,16 @@ 
		reg = <0 0x10200100 0 0x1c>;

		reg = <0 0x10200100 0 0x1c>;

	};

	};





	iommu: mmsys_iommu@10205000 {

		compatible = "mediatek,mt2701-m4u";

		reg = <0 0x10205000 0 0x1000>;

		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&infracfg CLK_INFRA_M4U>;

		clock-names = "bclk";

		mediatek,larbs = <&larb0 &larb1 &larb2>;

		#iommu-cells = <1>;

	};



	apmixedsys: syscon@10209000 {

	apmixedsys: syscon@10209000 {

		compatible = "mediatek,mt2701-apmixedsys", "syscon";

		compatible = "mediatek,mt2701-apmixedsys", "syscon";

		reg = <0 0x10209000 0 0x1000>;

		reg = <0 0x10209000 0 0x1000>;
@@ -233,18 +253,48 @@ 
		#clock-cells = <1>;

		#clock-cells = <1>;

	};

	};





	larb0: larb@14010000 {

		compatible = "mediatek,mt2701-smi-larb";

		reg = <0 0x14010000 0 0x1000>;

		mediatek,smi = <&smi_common>;

		clocks = <&mmsys CLK_MM_SMI_LARB0>,

			 <&mmsys CLK_MM_SMI_LARB0>;

		clock-names = "apb", "smi";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;

	};



	imgsys: syscon@15000000 {

	imgsys: syscon@15000000 {

		compatible = "mediatek,mt2701-imgsys", "syscon";

		compatible = "mediatek,mt2701-imgsys", "syscon";

		reg = <0 0x15000000 0 0x1000>;

		reg = <0 0x15000000 0 0x1000>;

		#clock-cells = <1>;

		#clock-cells = <1>;

	};

	};





	larb2: larb@15001000 {

		compatible = "mediatek,mt2701-smi-larb";

		reg = <0 0x15001000 0 0x1000>;

		mediatek,smi = <&smi_common>;

		clocks = <&imgsys CLK_IMG_SMI_COMM>,

			 <&imgsys CLK_IMG_SMI_COMM>;

		clock-names = "apb", "smi";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;

	};



	vdecsys: syscon@16000000 {

	vdecsys: syscon@16000000 {

		compatible = "mediatek,mt2701-vdecsys", "syscon";

		compatible = "mediatek,mt2701-vdecsys", "syscon";

		reg = <0 0x16000000 0 0x1000>;

		reg = <0 0x16000000 0 0x1000>;

		#clock-cells = <1>;

		#clock-cells = <1>;

	};

	};





	larb1: larb@16010000 {

		compatible = "mediatek,mt2701-smi-larb";

		reg = <0 0x16010000 0 0x1000>;

		mediatek,smi = <&smi_common>;

		clocks = <&vdecsys CLK_VDEC_CKGEN>,

			 <&vdecsys CLK_VDEC_LARB>;

		clock-names = "apb", "smi";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;

	};



	hifsys: syscon@1a000000 {

	hifsys: syscon@1a000000 {

		compatible = "mediatek,mt2701-hifsys", "syscon";

		compatible = "mediatek,mt2701-hifsys", "syscon";

		reg = <0 0x1a000000 0 0x1000>;

		reg = <0 0x1a000000 0 0x1000>;