Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0ce08da0 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "msm: camera: csiphy: Clean up bringup seq for 3phase operation"

parents e8888c1a 85c41e2a

drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_core.c

+70 −3
Original line number Diff line number Diff line
@@ -224,13 +224,18 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, 
	csiphy_dev->csiphy_info.csiphy_3phase =

		cam_cmd_csiphy_info->csiphy_3phase;

	csiphy_dev->csiphy_info.combo_mode |= cam_cmd_csiphy_info->combo_mode;

	if (cam_cmd_csiphy_info->combo_mode == 1)

	if (cam_cmd_csiphy_info->combo_mode == 1) {

		csiphy_dev->csiphy_info.settle_time_combo_sensor =

			cam_cmd_csiphy_info->settle_time;

	else

		csiphy_dev->csiphy_info.data_rate_combo_sensor =

			cam_cmd_csiphy_info->data_rate;

	} else {

		csiphy_dev->csiphy_info.settle_time =

			cam_cmd_csiphy_info->settle_time;

	csiphy_dev->csiphy_info.data_rate = cam_cmd_csiphy_info->data_rate;

		csiphy_dev->csiphy_info.data_rate =

			cam_cmd_csiphy_info->data_rate;

	}





	if (cam_cmd_csiphy_info->secure_mode == 1)

		cam_csiphy_update_secure_info(csiphy_dev,
@@ -252,6 +257,65 @@ void cam_csiphy_cphy_irq_config(struct csiphy_device *csiphy_dev) 
			csiphy_dev->ctrl_reg->csiphy_irq_reg[i].reg_addr);

}



void cam_csiphy_cphy_data_rate_config(struct csiphy_device *csiphy_device)

{

	int i = 0, j = 0;

	uint64_t phy_data_rate = 0;

	void __iomem *csiphybase = NULL;

	ssize_t num_table_entries = 0;

	struct data_rate_settings_t *settings_table = NULL;



	if ((csiphy_device == NULL) ||

		(csiphy_device->ctrl_reg == NULL) ||

		(csiphy_device->ctrl_reg->data_rates_settings_table == NULL)) {

		CAM_DBG(CAM_CSIPHY,

			"Data rate specific register table not found");

		return;

	}



	phy_data_rate = csiphy_device->csiphy_info.data_rate;

	csiphybase =

		csiphy_device->soc_info.reg_map[0].mem_base;

	settings_table =

		csiphy_device->ctrl_reg->data_rates_settings_table;

	num_table_entries =

		settings_table->num_data_rate_settings;



	CAM_DBG(CAM_CSIPHY, "required data rate : %llu", phy_data_rate);

	for (i = 0; i < num_table_entries; i++) {

		struct data_rate_reg_info_t *drate_settings =

			settings_table->data_rate_settings;

		uint64_t bandwidth =

			drate_settings[i].bandwidth;

		ssize_t  num_reg_entries =

		drate_settings[i].data_rate_reg_array_size;



		if (phy_data_rate > bandwidth) {

			CAM_DBG(CAM_CSIPHY,

					"Skipping table [%d] %llu required: %llu",

					i, bandwidth, phy_data_rate);

			continue;

		}



		CAM_DBG(CAM_CSIPHY,

			"table[%d] BW : %llu Selected", i, bandwidth);

		for (j = 0; j < num_reg_entries; j++) {

			uint32_t reg_addr =

			drate_settings[i].csiphy_data_rate_regs[j].reg_addr;



			uint32_t reg_data =

			drate_settings[i].csiphy_data_rate_regs[j].reg_data;



			CAM_DBG(CAM_CSIPHY,

				"writing reg : %x val : %x",

						reg_addr, reg_data);

			cam_io_w_mb(reg_data,

				csiphybase + reg_addr);

		}

		break;

	}

}



void cam_csiphy_cphy_irq_disable(struct csiphy_device *csiphy_dev)

{

	int32_t i;
@@ -459,6 +523,9 @@ int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev) 
		lane_pos++;

	}



	if (csiphy_dev->csiphy_info.csiphy_3phase)

		cam_csiphy_cphy_data_rate_config(csiphy_dev);



	cam_csiphy_cphy_irq_config(csiphy_dev);



	return rc;

drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h

+68 −29
Original line number Diff line number Diff line
@@ -36,6 +36,8 @@ 


#define MAX_LANES                   5

#define MAX_SETTINGS_PER_LANE       43

#define MAX_DATA_RATES              3

#define MAX_DATA_RATE_REGS          30



#define MAX_REGULATOR         5

#define CAMX_CSIPHY_DEV_NAME "cam-csiphy-driver"
@@ -145,6 +147,32 @@ struct csiphy_reg_t { 
	uint32_t csiphy_param_type;

};



struct csiphy_device;



/*

 * struct data_rate_reg_info_t

 * @bandwidth: max bandwidth supported by this reg settings

 * @data_rate_reg_array_size: number of reg value pairs in the array

 * @csiphy_data_rate_regs: array of data rate specific reg value pairs

 */

struct data_rate_reg_info_t {

	uint64_t bandwidth;

	ssize_t  data_rate_reg_array_size;

	struct csiphy_reg_t csiphy_data_rate_regs[MAX_DATA_RATE_REGS];

};



/**

 * struct data_rate_settings_t

 * @num_data_rate_settings: number of valid settings

 *                          present in the data rate settings array

 * @data_rate_settings: array of regsettings which are specific to

 *                      data rate

 */

struct data_rate_settings_t {

	ssize_t num_data_rate_settings;

	struct data_rate_reg_info_t data_rate_settings[MAX_DATA_RATES];

};



/**

 * struct csiphy_ctrl_t

 * @csiphy_reg: Register address
@@ -156,6 +184,12 @@ struct csiphy_reg_t { 
 * @csiphy_3ph_reg: 3phase register set

 * @csiphy_2ph_3ph_mode_reg:

 *     2 phase 3phase combo register set

 * @getclockvoting: function pointer which

 *      is used to find the clock voting

 *      for the sensor output data rate

 * @data_rate_settings_table:

 *      Table which maintains the resgister

 *      settings specific to data rate

 */

struct csiphy_ctrl_t {

	struct csiphy_reg_parms_t csiphy_reg;
@@ -166,6 +200,8 @@ struct csiphy_ctrl_t { 
	struct csiphy_reg_t (*csiphy_2ph_combo_mode_reg)[MAX_SETTINGS_PER_LANE];

	struct csiphy_reg_t (*csiphy_3ph_reg)[MAX_SETTINGS_PER_LANE];

	struct csiphy_reg_t (*csiphy_2ph_3ph_mode_reg)[MAX_SETTINGS_PER_LANE];

	enum   cam_vote_level (*getclockvoting)(struct csiphy_device *phy_dev);

	struct data_rate_settings_t *data_rates_settings_table;

};



/**
@@ -180,6 +216,8 @@ struct csiphy_ctrl_t { 
 * @settle_time   :  Settling time in ms

 * @settle_time_combo_sensor   :  Settling time in ms

 * @data_rate     :  Data rate in mbps

 * @data_rate_combo_sensor: data rate of combo sensor

 *                          in the the same phy

 *

 */

struct cam_csiphy_param {
@@ -192,6 +230,7 @@ struct cam_csiphy_param { 
	uint64_t    settle_time;

	uint64_t    settle_time_combo_sensor;

	uint64_t    data_rate;

	uint64_t    data_rate_combo_sensor;

};



/**
@@ -216,8 +255,7 @@ struct cam_csiphy_param { 
 * @clk_lane:                   Clock lane

 * @acquire_count:              Acquire device count

 * @start_dev_count:            Start count

 * @is_acquired_dev_combo_mode:

 *    Flag that mentions whether already acquired

 * @is_acquired_dev_combo_mode: Flag that mentions whether already acquired

 *                              device is for combo mode

 * @soc_info:                   SOC information

 * @cpas_handle:                CPAS handle
@@ -236,6 +274,7 @@ struct csiphy_device { 
	int32_t ref_count;

	uint16_t lane_mask[MAX_CSIPHY];

	uint8_t is_csiphy_3phase_hw;

	uint8_t is_divisor_32_comp;

	uint8_t num_irq_registers;

	struct cam_subdev v4l2_dev_str;

	struct cam_csiphy_param csiphy_info;

drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c

+75 −2
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 */



#include "cam_csiphy_soc.h"
@@ -11,6 +11,9 @@ 
#include "include/cam_csiphy_1_2_1_hwreg.h"

#include "include/cam_csiphy_2_0_hwreg.h"



#define CSIPHY_DIVISOR_16           16

#define CSIPHY_DIVISOR_32           32

#define CSIPHY_DIVISOR_8             8

#define BYTES_PER_REGISTER           4

#define NUM_REGISTER_PER_LINE        4

#define REG_OFFSET(__start, __i)    ((__start) + ((__i) * BYTES_PER_REGISTER))
@@ -73,10 +76,62 @@ int32_t cam_csiphy_mem_dmp(struct cam_hw_soc_info *soc_info) 
	return rc;

}



enum cam_vote_level get_clk_vote_default(struct csiphy_device *csiphy_dev)

{

	CAM_DBG(CAM_CSIPHY, "voting for SVS");

	return CAM_SVS_VOTE;

}



enum cam_vote_level get_clk_voting_dynamic(struct csiphy_device *csiphy_dev)

{

	uint32_t cam_vote_level = 0;

	uint32_t last_valid_vote = 0;

	struct cam_hw_soc_info *soc_info;

	uint64_t phy_data_rate = csiphy_dev->csiphy_info.data_rate;



	soc_info = &csiphy_dev->soc_info;



	if (csiphy_dev->is_acquired_dev_combo_mode)

		phy_data_rate = max(phy_data_rate,

			csiphy_dev->csiphy_info.data_rate_combo_sensor);



	if (csiphy_dev->csiphy_info.csiphy_3phase) {

		if (csiphy_dev->is_divisor_32_comp)

			do_div(phy_data_rate, CSIPHY_DIVISOR_32);

		else

			do_div(phy_data_rate, CSIPHY_DIVISOR_16);

	} else {

		do_div(phy_data_rate, CSIPHY_DIVISOR_8);

	}



	 /* round off to next integer */

	phy_data_rate += 1;



	for (cam_vote_level = 0;

			cam_vote_level < CAM_MAX_VOTE; cam_vote_level++) {

		if (soc_info->clk_level_valid[cam_vote_level] != true)

			continue;



		if (soc_info->clk_rate[cam_vote_level][0] >

				phy_data_rate) {

			CAM_DBG(CAM_CSIPHY,

				"match detected %s : %llu:%d level : %d",

				soc_info->clk_name[0],

				phy_data_rate,

				soc_info->clk_rate[cam_vote_level][0],

				cam_vote_level);

			return cam_vote_level;

		}

		last_valid_vote = cam_vote_level;

	}

	return last_valid_vote;

}



int32_t cam_csiphy_enable_hw(struct csiphy_device *csiphy_dev)

{

	int32_t rc = 0;

	struct cam_hw_soc_info   *soc_info;

	enum cam_vote_level vote_level = CAM_SVS_VOTE;



	soc_info = &csiphy_dev->soc_info;
@@ -86,8 +141,9 @@ int32_t cam_csiphy_enable_hw(struct csiphy_device *csiphy_dev) 
		return rc;

	}



	vote_level = csiphy_dev->ctrl_reg->getclockvoting(csiphy_dev);

	rc = cam_soc_util_enable_platform_resource(soc_info, true,

		CAM_SVS_VOTE, ENABLE_IRQ);

		vote_level, ENABLE_IRQ);

	if (rc < 0) {

		CAM_ERR(CAM_CSIPHY, "failed to enable platform resources %d",

			rc);
@@ -168,9 +224,12 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, 
		csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_1_0;

		csiphy_dev->ctrl_reg->csiphy_reset_reg = csiphy_reset_reg_1_0;

		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_0;

		csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default;

		csiphy_dev->hw_version = CSIPHY_VERSION_V10;

		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW;

		csiphy_dev->is_divisor_32_comp = false;

		csiphy_dev->clk_lane = 0;

		csiphy_dev->ctrl_reg->data_rates_settings_table = NULL;

	} else if (of_device_is_compatible(soc_info->dev->of_node,

		"qcom,csiphy-v1.1")) {

		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_1_reg;
@@ -185,9 +244,12 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, 
		csiphy_dev->ctrl_reg->csiphy_reset_reg =

			csiphy_reset_reg_1_1;

		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_1;

		csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default;

		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW;

		csiphy_dev->is_divisor_32_comp = false;

		csiphy_dev->hw_version = CSIPHY_VERSION_V11;

		csiphy_dev->clk_lane = 0;

		csiphy_dev->ctrl_reg->data_rates_settings_table = NULL;

	} else if (of_device_is_compatible(soc_info->dev->of_node,

		"qcom,csiphy-v1.2")) {

		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_reg;
@@ -200,10 +262,14 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, 
			csiphy_common_reg_1_2;

		csiphy_dev->ctrl_reg->csiphy_reset_reg =

			csiphy_reset_reg_1_2;

		csiphy_dev->ctrl_reg->getclockvoting = get_clk_voting_dynamic;

		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2;

		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW;

		csiphy_dev->is_divisor_32_comp = true;

		csiphy_dev->hw_version = CSIPHY_VERSION_V12;

		csiphy_dev->clk_lane = 0;

		csiphy_dev->ctrl_reg->data_rates_settings_table =

			&data_rate_delta_table;

	} else if (of_device_is_compatible(soc_info->dev->of_node,

		"qcom,csiphy-v1.2.1")) {

		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_1_reg;
@@ -217,9 +283,13 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, 
		csiphy_dev->ctrl_reg->csiphy_reset_reg =

			csiphy_reset_reg_1_2_1;

		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2_1;

		csiphy_dev->ctrl_reg->getclockvoting = get_clk_voting_dynamic;

		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW;

		csiphy_dev->is_divisor_32_comp = true;

		csiphy_dev->hw_version = CSIPHY_VERSION_V121;

		csiphy_dev->clk_lane = 0;

		csiphy_dev->ctrl_reg->data_rates_settings_table =

			&data_rate_delta_table_1_2_1;

	} else if (of_device_is_compatible(soc_info->dev->of_node,

		"qcom,csiphy-v2.0")) {

		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v2_0_reg;
@@ -231,9 +301,12 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, 
		csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_2_0;

		csiphy_dev->ctrl_reg->csiphy_reset_reg = csiphy_reset_reg_2_0;

		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v2_0;

		csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default;

		csiphy_dev->hw_version = CSIPHY_VERSION_V20;

		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW;

		csiphy_dev->is_divisor_32_comp = false;

		csiphy_dev->clk_lane = 0;

		csiphy_dev->ctrl_reg->data_rates_settings_table = NULL;

	} else {

		CAM_ERR(CAM_CSIPHY, "invalid hw version : 0x%x",

			csiphy_dev->hw_version);

drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h

+95 −17
Original line number Diff line number Diff line
@@ -12,10 +12,10 @@ struct csiphy_reg_parms_t csiphy_v1_2_1 = { 
	.mipi_csiphy_interrupt_status0_addr = 0x8B0,

	.mipi_csiphy_interrupt_clear0_addr = 0x858,

	.mipi_csiphy_glbl_irq_cmd_addr = 0x828,

	.csiphy_common_array_size = 4,

	.csiphy_reset_array_size = 4,

	.csiphy_common_array_size = 6,

	.csiphy_reset_array_size = 5,

	.csiphy_2ph_config_array_size = 21,

	.csiphy_3ph_config_array_size = 38,

	.csiphy_3ph_config_array_size = 34,

	.csiphy_2ph_clock_lane = 0x1,

	.csiphy_2ph_combo_ck_ln = 0x10,

};
@@ -23,14 +23,17 @@ struct csiphy_reg_parms_t csiphy_v1_2_1 = { 
struct csiphy_reg_t csiphy_common_reg_1_2_1[] = {

	{0x0814, 0xd5, 0x00, CSIPHY_LANE_ENABLE},

	{0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x081C, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x081C, 0x02, 0x00, CSIPHY_2PH_REGS},

	{0x081C, 0x52, 0x00, CSIPHY_3PH_REGS},

	{0x0800, 0x02, 0x00, CSIPHY_2PH_REGS},

	{0x0800, 0x0E, 0x00, CSIPHY_3PH_REGS},

};



struct csiphy_reg_t csiphy_reset_reg_1_2_1[] = {

	{0x0814, 0x00, 0x05, CSIPHY_LANE_ENABLE},

	{0x0818, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x081C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x0800, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

};
@@ -289,7 +292,6 @@ struct csiphy_reg_t 
struct

csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {

	{

		{0x015C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0990, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0994, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0998, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -298,7 +300,6 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0998, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x098C, 0xAF, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0168, 0xAC, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x016C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x010C, 0x07, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},

		{0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
@@ -313,7 +314,6 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0144, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0164, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -325,11 +325,9 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0988, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0980, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x09B0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x09B4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},

	},

	{

		{0x035C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0A90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0A94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0A98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -338,7 +336,6 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0A98, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0A8C, 0xBF, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0368, 0xAC, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x036C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x030C, 0x07, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},

		{0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
@@ -353,7 +350,6 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0344, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0364, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -365,11 +361,9 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0A88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0A80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0AB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0AB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},

	},

	{

		{0x055C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0B90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0B94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0B98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -378,7 +372,6 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0B98, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0B8C, 0xAF, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0568, 0xAC, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x056C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x050C, 0x07, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},

		{0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
@@ -393,7 +386,6 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0544, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0564, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -405,9 +397,95 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0B88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0B80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0BB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0BB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},

	},

};



struct data_rate_settings_t data_rate_delta_table_1_2_1 = {

	.num_data_rate_settings = 3,

	.data_rate_settings = {

		{

			/* (2.5 * 10**3 * 2.28) rounded value*/

			.bandwidth = 5700000000,

			.data_rate_reg_array_size = 12,

			.csiphy_data_rate_regs = {

				{0x15C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x35C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x55C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x9B4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xAB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xBB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x144, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x344, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x544, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x16C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x36C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x56C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS},

			}

		},

		{

			/* (3.5 * 10**3 * 2.28) rounded value */

			.bandwidth = 7980000000,

			.data_rate_reg_array_size = 24,

			.csiphy_data_rate_regs = {

				{0x15C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x35C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x55C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x9B4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xAB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xBB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x9B0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xAB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xBB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x144, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x344, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x544, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x13C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x33C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x53C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x140, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x340, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x540, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x16C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x36C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x56C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},

			},

		},

		{

			/* (4.5 * 10**3 * 2.28) rounded value */

			.bandwidth = 10260000000,

			.data_rate_reg_array_size = 24,

			.csiphy_data_rate_regs = {

				{0x15C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x35C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x55C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x9B4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xAB4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xBB4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x9B0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xAB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xBB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x144, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x344, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x544, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x13C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x33C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x53C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x140, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x340, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x540, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x16C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x36C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x56C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},

			},

		}

	}

};



#endif /* _CAM_CSIPHY_1_2_1_HWREG_H_ */

drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h

+87 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 */



#ifndef _CAM_CSIPHY_1_2_HWREG_H_
@@ -389,4 +389,90 @@ csiphy_reg_t csiphy_3ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
	},

};



struct data_rate_settings_t data_rate_delta_table = {

	.num_data_rate_settings = 3,

	.data_rate_settings = {

		{

			/* (2.5 * 10**3 * 2.28) rounded value*/

			.bandwidth = 5700000000,

			.data_rate_reg_array_size = 12,

			.csiphy_data_rate_regs = {

				{0x15C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x35C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x55C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x9B4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xAB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xBB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x144, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x344, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x544, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x16C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x36C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x56C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS},

			}

		},

		{

			/* (3.5 * 10**3 * 2.28) rounded value */

			.bandwidth = 7980000000,

			.data_rate_reg_array_size = 24,

			.csiphy_data_rate_regs = {

				{0x15C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x35C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x55C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x9B4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xAB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xBB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x9B0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xAB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xBB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x144, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x344, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x544, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x13C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x33C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x53C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x140, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x340, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x540, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x16C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x36C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x56C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},

			},

		},

		{

			/* (4.5 * 10**3 * 2.28) rounded value */

			.bandwidth = 10260000000,

			.data_rate_reg_array_size = 24,

			.csiphy_data_rate_regs = {

				{0x15C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x35C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x55C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x9B4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xAB4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xBB4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x9B0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xAB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xBB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x144, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x344, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x544, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x13C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x33C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x53C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x140, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x340, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x540, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x16C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x36C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x56C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},

			},

		}

	}

};

#endif /* _CAM_CSIPHY_1_2_HWREG_H_ */