Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc (0a95d92c) · Commits · e / devices / android_kernel_oneplus_sm7250

Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt

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		* Freescale PQ3 and QorIQ based Cache SRAM

		Freescale's mpc85xx and some QorIQ platforms provide an
		option of configuring a part of (or full) cache memory
		as SRAM. This cache SRAM representation in the device
		tree should be done as under:-

		Required properties:

		- compatible : should be "fsl,p2020-cache-sram"
		- fsl,cache-sram-ctlr-handle : points to the L2 controller
		- reg : offset and length of the cache-sram.

		Example:

		cache-sram@fff00000 {
		fsl,cache-sram-ctlr-handle = <&L2>;
		reg = <0 0xfff00000 0 0x10000>;
		compatible = "fsl,p2020-cache-sram";
		};

Documentation/devicetree/bindings/powerpc/fsl/mpic.txt

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		* OpenPIC and its interrupt numbers on Freescale's e500/e600 cores

		The OpenPIC specification does not specify which interrupt source has to
		become which interrupt number. This is up to the software implementation
		of the interrupt controller. The only requirement is that every
		interrupt source has to have an unique interrupt number / vector number.
		To accomplish this the current implementation assigns the number zero to
		the first source, the number one to the second source and so on until
		all interrupt sources have their unique number.
		Usually the assigned vector number equals the interrupt number mentioned
		in the documentation for a given core / CPU. This is however not true
		for the e500 cores (MPC85XX CPUs) where the documentation distinguishes
		between internal and external interrupt sources and starts counting at
		zero for both of them.

		So what to write for external interrupt source X or internal interrupt
		source Y into the device tree? Here is an example:

		The memory map for the interrupt controller in the MPC8544[0] shows,
		that the first interrupt source starts at 0x5_0000 (PIC Register Address
		Map-Interrupt Source Configuration Registers). This source becomes the
		number zero therefore:
		External interrupt 0 = interrupt number 0
		External interrupt 1 = interrupt number 1
		External interrupt 2 = interrupt number 2
		...
		Every interrupt number allocates 0x20 bytes register space. So to get
		its number it is sufficient to shift the lower 16bits to right by five.
		So for the external interrupt 10 we have:
		0x0140 >> 5 = 10

		After the external sources, the internal sources follow. The in core I2C
		controller on the MPC8544 for instance has the internal source number
		27. Oo obtain its interrupt number we take the lower 16bits of its memory
		address (0x5_0560) and shift it right:
		0x0560 >> 5 = 43

		Therefore the I2C device node for the MPC8544 CPU has to have the
		interrupt number 43 specified in the device tree.

		[0] MPC8544E PowerQUICCTM III, Integrated Host Processor Family Reference Manual
		MPC8544ERM Rev. 1 10/2007
		=====================================================================
		Freescale MPIC Interrupt Controller Node
		Copyright (C) 2010,2011 Freescale Semiconductor Inc.
		=====================================================================

		The Freescale MPIC interrupt controller is found on all PowerQUICC
		and QorIQ processors and is compatible with the Open PIC. The
		notable difference from Open PIC binding is the addition of 2
		additional cells in the interrupt specifier defining interrupt type
		information.

		PROPERTIES

		- compatible
		Usage: required
		Value type: <string>
		Definition: Shall include "fsl,mpic". Freescale MPIC
		controllers compatible with this binding have Block
		Revision Registers BRR1 and BRR2 at offset 0x0 and
		0x10 in the MPIC.

		- reg
		Usage: required
		Value type: <prop-encoded-array>
		Definition: A standard property. Specifies the physical
		offset and length of the device's registers within the
		CCSR address space.

		- interrupt-controller
		Usage: required
		Value type: <empty>
		Definition: Specifies that this node is an interrupt
		controller

		- #interrupt-cells
		Usage: required
		Value type: <u32>
		Definition: Shall be 2 or 4. A value of 2 means that interrupt
		specifiers do not contain the interrupt-type or type-specific
		information cells.

		- #address-cells
		Usage: required
		Value type: <u32>
		Definition: Shall be 0.

		- pic-no-reset
		Usage: optional
		Value type: <empty>
		Definition: The presence of this property specifies that the
		MPIC must not be reset by the client program, and that
		the boot program has initialized all interrupt source
		configuration registers to a sane state-- masked or
		directed at other cores. This ensures that the client
		program will not receive interrupts for sources not belonging
		to the client. The presence of this property also mandates
		that any initialization related to interrupt sources shall
		be limited to sources explicitly referenced in the device tree.

		INTERRUPT SPECIFIER DEFINITION

		Interrupt specifiers consists of 4 cells encoded as
		follows:

		<1st-cell> interrupt-number

		Identifies the interrupt source. The meaning
		depends on the type of interrupt.

		Note: If the interrupt-type cell is undefined
		(i.e. #interrupt-cells = 2), this cell
		should be interpreted the same as for
		interrupt-type 0-- i.e. an external or
		normal SoC device interrupt.

		<2nd-cell> level-sense information, encoded as follows:
		0 = low-to-high edge triggered
		1 = active low level-sensitive
		2 = active high level-sensitive
		3 = high-to-low edge triggered

		<3rd-cell> interrupt-type

		The following types are supported:

		0 = external or normal SoC device interrupt

		The interrupt-number cell contains
		the SoC device interrupt number. The
		type-specific cell is undefined. The
		interrupt-number is derived from the
		MPIC a block of registers referred to as
		the "Interrupt Source Configuration Registers".
		Each source has 32-bytes of registers
		(vector/priority and destination) in this
		region. So interrupt 0 is at offset 0x0,
		interrupt 1 is at offset 0x20, and so on.

		1 = error interrupt

		The interrupt-number cell contains
		the SoC device interrupt number for
		the error interrupt. The type-specific
		cell identifies the specific error
		interrupt number.

		2 = MPIC inter-processor interrupt (IPI)

		The interrupt-number cell identifies
		the MPIC IPI number. The type-specific
		cell is undefined.

		3 = MPIC timer interrupt

		The interrupt-number cell identifies
		the MPIC timer number. The type-specific
		cell is undefined.

		<4th-cell> type-specific information

		The type-specific cell is encoded as follows:

		- For interrupt-type 1 (error interrupt),
		the type-specific cell contains the
		bit number of the error interrupt in the
		Error Interrupt Summary Register.

		EXAMPLE 1
		/*
		* mpic interrupt controller with 4 cells per specifier
		*/
		mpic: pic@40000 {
		compatible = "fsl,mpic";
		interrupt-controller;
		#interrupt-cells = <4>;
		#address-cells = <0>;
		reg = <0x40000 0x40000>;
		};

		EXAMPLE 2
		/*
		* The MPC8544 I2C controller node has an internal
		* interrupt number of 27. As per the reference manual
		* this corresponds to interrupt source configuration
		* registers at 0x5_0560.
		*
		* The interrupt source configuration registers begin
		* at 0x5_0000.
		*
		* To compute the interrupt specifier interrupt number
		*
		* 0x560 >> 5 = 43
		*
		* The interrupt source configuration registers begin
		* at 0x5_0000, and so the i2c vector/priority registers
		* are at 0x5_0560.
		*/
		i2c@3000 {
		#address-cells = <1>;
		#size-cells = <0>;
		cell-index = <0>;
		compatible = "fsl-i2c";
		reg = <0x3000 0x100>;
		interrupts = <43 2>;
		interrupt-parent = <&mpic>;
		dfsrr;
		};


		EXAMPLE 3
		/*
		* Definition of a node defining the 4
		* MPIC IPI interrupts. Note the interrupt
		* type of 2.
		*/
		ipi@410a0 {
		compatible = "fsl,mpic-ipi";
		reg = <0x40040 0x10>;
		interrupts = <0 0 2 0
		1 0 2 0
		2 0 2 0
		3 0 2 0>;
		};

		EXAMPLE 4
		/*
		* Definition of a node defining the MPIC
		* global timers. Note the interrupt
		* type of 3.
		*/
		timer0: timer@41100 {
		compatible = "fsl,mpic-global-timer";
		reg = <0x41100 0x100>;
		interrupts = <0 0 3 0
		1 0 3 0
		2 0 3 0
		3 0 3 0>;
		};

		EXAMPLE 5
		/*
		* Definition of an error interrupt (interupt type 1).
		* SoC interrupt number is 16 and the specific error
		* interrupt bit in the error interrupt summary register
		* is 23.
		*/
		memory-controller@8000 {
		compatible = "fsl,p4080-memory-controller";
		reg = <0x8000 0x1000>;
		interrupts = <16 2 1 23>;
		};

Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt

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		@@ -5,14 +5,21 @@ Required properties:
		first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
		etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
		the parent type.

		- reg : should contain the address and the length of the shared message
		interrupt register set.

		- msi-available-ranges: use <start count> style section to define which
		msi interrupt can be used in the 256 msi interrupts. This property is
		optional, without this, all the 256 MSI interrupts can be used.
		Each available range must begin and end on a multiple of 32 (i.e.
		no splitting an individual MSI register or the associated PIC interrupt).

		- interrupts : each one of the interrupts here is one entry per 32 MSIs,
		and routed to the host interrupt controller. the interrupts should
		be set as edge sensitive.
		be set as edge sensitive. If msi-available-ranges is present, only
		the interrupts that correspond to available ranges shall be present.

		- interrupt-parent: the phandle for the interrupt controller
		that services interrupts for this device. for 83xx cpu, the interrupts
		are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed

Documentation/kernel-parameters.txt

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		@@ -626,6 +626,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
		disable= [IPV6]
		See Documentation/networking/ipv6.txt.

		disable_ddw [PPC/PSERIES]
		Disable Dynamic DMA Window support. Use this if
		to workaround buggy firmware.

		disable_ipv6= [IPV6]
		See Documentation/networking/ipv6.txt.

arch/powerpc/Kconfig

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		@@ -134,6 +134,7 @@ config PPC
		select HAVE_GENERIC_HARDIRQS
		select HAVE_SPARSE_IRQ
		select IRQ_PER_CPU
		select GENERIC_HARDIRQS_NO_DEPRECATED

		config EARLY_PRINTK
		bool